Low substrate/lattice temperature (< 300 K) operation of n-MOSFET has been effectively studied by device research and integration professionals in CMOS logic and analog products from the early 1970s. The author of this book previously composed an e-book in this area where he and his co-authors performed original simulation and modeling work on MOSFET threshold voltage and demonstrated that through efficient manipulation of threshold voltage values at lower substrate temperatures, superior degrees of reduction of subthreshold and off-state leakage current can be implemented in high-density logic and microprocessor chips fabricated in a silicon die. In this book, the author explores other device parameters such as channel inversion carrier mobility and its characteristic evolution as temperature on the die varies from 100-300 K. Channel mobility affects both on-state drain current and subthreshold drain current and both drain current behaviors at lower temperatures have been modeled accurately and simulated for a 1 ??m channel length n-MOSFET. In addition, subthreshold slope which is an indicator of how speedily the device drain current can be switched between near off current and maximum drain current is an important device attribute to model at lower operating substrate temperatures. This book is the first to illustrate the fact that a single subthreshold slope value which is generally reported in textbook plots and research articles, is erroneous and at lower gate voltage below inversion, subthreshold slope value exhibits a variation tendency on applied gate voltage below threshold, i.e., varying depletion layer and vertical field induced surface band bending variations at the MOSFET channel surface. The author also will critically review the state-of-the art effectiveness of certain device architectures presently prevalent in the semiconductor industry below 45 nm node from the perspectives of device physical analysis at lower substrate temperature operating conditions. The book concludes with an emphasis on modeling simulations, inviting the device professionals to meet the performance bottlenecks emanating from inceptives present at these lower temperatures of operation of today's 10 nm device architectures.

Autorentext

Nabil Shovon Ashraf was born in Dhaka, Bangladesh, in 1974. He obtained his Bachelor's degree in Electrical Engineering (EE) from Indian Institute of Technology Kanpur, India, in 1997, Master's degree in EE from University of Central Florida, Orlando, Florida, in 1999, and Doctorate degree in EE from Arizona State University, Tempe, Arizona, in 2011. He was a post doctoral researcher in the department of electrical engineering of Arizona State University from 2011-2014. He was employed as design engineer in RF Monolithics Inc., a surface acoustic wave (SAW) based filter design company in Dallas, Texas, from 1999-2001. From 2003 till 2006 he served on the faculty of the department of Electrical & Electronic Engineering of Islamic University of Technology, Gazipur, Bangladesh, as Assistant Professor. In fall 2014, he became Assistant Professor in the department of Electrical and Computer Engineering (ECE) of North South University, Dhaka, Bangladesh. He has been listed in Marquis Who's Who in America in 2016 (70th platinum edition) and also in 2015 (69th edition). Dr. Ashraf has, to date, published six peer reviewed journal papers (two IEEE EDS society) and around 14 conference papers (three IEEE EDS society). He has also contributed to two book chapters on interface trap-induced reliability aspects (threshold voltage fluctuations) of nanoscale devices. He specializes in the area of device physics and modeling analysis of scaled devices for enabling improved device performance at the scaled node of current MOSFET device architectures. Shawon Alam successfully completed his Bachelor's of Science in Electrical and Electronic Engineering from North South University in August 2015, and has performed research (2014âEUR"2015) concentrating on nanoscale nMOSFET device modeling on threshold voltage with the impact of temperature (100K-500K). Later, he joined an internship program at a multinational telecommunications company for a period of four months. He was involved with many extra-curricular and co-curricular activities like sports, social service, and a teaching assistantship during his graduate program. Presently, he is working as a network engineer in a renowned organization involved with international internet gateway (IIG) as well as internet service provider (ISP). In the future, he is willing to do further research on the MOSFET device. Mohaiminul Alam, a distinguished graduate with a Bachelor's of Science in Electrical and Electronic Engineering from North South University, has performed research (2014-2015) concentrating on CMOS device modeling, projecting the impact of temperature (100KâEUR"500K) on threshold voltage. Later, he joined an internship program at a telecommunications company. He is currently working as a project system and development engineer in an organization involved with the research and development program of solar products and solar solutions.

Klappentext

Low substrate/lattice temperature (< 300 K) operation of n-MOSFET has been effectively studied by device research and integration professionals in CMOS logic and analog products from the early 1970s. The author of this book previously composed an e-book in this area where he and his co-authors performed original simulation and modeling work on MOSFET threshold voltage and demonstrated that through efficient manipulation of threshold voltage values at lower substrate temperatures, superior degrees of reduction of subthreshold and off-state leakage current can be implemented in high-density logic and microprocessor chips fabricated in a silicon die. In this book, the author explores other device parameters such as channel inversion carrier mobility and its characteristic evolution as temperature on the die varies from 100-300 K. Channel mobility affects both on-state drain current and subthreshold drain current and both drain current behaviors at lower temperatures have been modeled accurately and simulated for a 1 ??m channel length n-MOSFET. In addition, subthreshold slope which is an indicator of how speedily the device drain current can be switched between near off current and maximum drain current is an important device attribute to model at lower operating substrate temperatures. This book is the first to illustrate the fact that a single subthreshold slope value which is generally reported in textbook plots and research articles, is erroneous and at lower gate voltage below inversion, subthreshold slope value exhibits a variation tendency on applied gate voltage below threshold, i.e., varying depletion layer and vertical field induced surface band bending variations at the MOSFET channel surface. The author also will critically review the state-of-the art effectiveness of certain device architectures presently prevalent in the semiconductor industry below 45 nm node from the perspectives of device physical analysis at lower substrate temperature operating conditions. The book concludes with an emphasis on modeling simulations, inviting the device professionals to meet the performance bottlenecks emanating from inceptives present at these lower temperatures of operation of today's 10 nm device architectures.

Inhalt
Preface.- Acknowledgments.- Introduction.- Historical Perspectives of Scaled MOSFET Evolution.- Simulation Results of On-State Drain Current and Subthreshold Drain Current at Substrate Temperatures Below 300 K.- Simulation Results on Substrate Mobility and On-Channel Mobility of Conventional Long-Channel ??-MOSFET at Substrate Temperatures 300 K and below.- Simulation Outcomes of Subthreshold Slope Factor or Coefficient for Different Substrate Temperatures at the Vicinity of a Subthreshold Region to D…