This book aims at describing in detail the different layout techniques for remarkably boosting the electrical performance and the ionizing radiation tolerance of planar Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs) without adding any costs to the current planar Complementary MOS (CMOS) integrated circuits (ICs) manufacturing processes. These innovative layout styles are based on pn junctions engineering between the drain/source and channel regions or simply MOSFET gate layout change. These interesting layout structures are capable of incorporating new effects in the MOSFET structures, such as the Longitudinal Corner Effect (LCE), the Parallel connection of MOSFETs with Different Channel Lengths Effect (PAMDLE), the Deactivation of the Parallel MOSFETs in the Bird's Beak Regions (DEPAMBBRE), and the Drain Leakage Current Reduction Effect (DLECRE), which are still seldom explored by the semiconductor and CMOS ICs industries. Several three-dimensional (3D) numerical simulations and experimental works are referenced in this book to show how these layout techniques can help the designers to reach the analog and digital CMOS ICs specifications with no additional cost. Furthermore, the electrical performance and ionizing radiation robustness of the analog and digital CMOS ICs can significantly be increased by using this gate layout approach.

Autorentext

Salvador Pinillos Gimenez was born in Sao Paulo, Brazil, in 1962. He received a graduate degree in Electrical Engineering from UMC University, Sao Paulo, Brazil, in 1984. He earned his M.S. (Microelectronics Laboratory, LME) and Ph.D. (Integrated Systems Laboratory, LSI) in Electrical Engineering from the University of Sao Paulo, Brazil, in 1990 and 2004, respectively. He worked as a Product Engineer at Dimep S.A (1987-1992), and Tracecom Telecommunications Systems S.A (1993). From 1994 to 1999, he worked at Ford (Electronic Division, after Visteon) in Guarulhos, Sao Paulo, Brazil, as a Component Engineer and Supply Quality Assurance and then Quality & Productivity Coordinator. Since 1999, he has been a professor and researcher at FEI University Center, Brazil, and became a full professor in 2010. He has authored textbooks on Microcontrollers and holds industrial patents on MOSFET with innovative gate geometries. His major fields of study include innovative non-standard MOSFETs structures, analog and digital CMOS ICs designs, and evolutionary electronic by developing analog CMOS ICs tools. Dr. Gimenez is a member of the Microelectronic Brazilian Society (SBMicro) and IEEE member (M'13). Since October 2015, he has participated on the editorial board (Associate Editor) of the Electronics Letters Journal (Institution of Engineering and Technology, IET - England, Wales, and Scotland).

Inhalt
Dedication.- Acknowledgments.- Introduction.- The Origin of the Innovative Layout Techniques for MOSFETS.- Diamond MOSFET (Hexagonal Gate Geometry).- Octo Layout Style (Octagonal Gate Shape) for MOSFET.- Ellipsoidal Layout Style for MOSFET.- Fish Layout Style ("