Low-Power Low-Voltage Sigma-Delta Modulators in Nanometer CMOS addresses the low-power low-voltage Sigma-Delta ADC design in nanometer CMOS technologies at both the circuit-level and the system level.

The low-power low-voltage Sigma-Delta modulator design at the circuit level is introduced. A design example is presented in this book. This design is the first published Sigma-Delta design in a 90-nm CMOS technology and reaches a very high figure-of-merit.

At the system level, a novel systematic study on the full feedforward Sigma-Delta topology is presented in this book. As a design example, a fourth-order single-loop full feedforward Sigma-Delta modulator design in a 130-nm pure digital CMOS technology is presented. This design is the first design using the full feedforward Sigma-Delta topology and reaches the highest conversion speed among all the 1-V Sigma-Delta modulators to date.

First published Sigma-Delta ADC design in a 90-nm CMOS technology Very high Figure-of-Merit achieved The 1-V full-feedforward Sigma-Delta topology

Autorentext
Prof. Michiel Steyaert received his Ph.D. degree in electronics from the Katholieke Universiteit Leuven (KUL) in June 1987. In 1988 he was an associated assistant professor at the U.C.L.A. From 1989 he joined the ESAT-MICAS group at the KUL, were he is now a Full Professor. His current research interests are in analog integrated circuits for high-frequency telecommunication systems and high performance analog signal processing. He authored or co-authored over 250 papers and co-authored over 5 books. He received the 1990 European Solid-State Circuits Conference Best Paper Award, the 1995 and 1997 ISSCC Evening Session Award, the 1999 IEEE Circuit and Systems Society Guillemin-Cauer Award and the 1991 NFWO Alcatel-Bell-Telephone award for innovative work in integrated circuits for telecommunications.

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Inhalt
ADCs in Nanometer CMOS Technologies.- Principle of ?-? ADC.- Low-Power Low-Voltage ?-? ADC Design in Nanometer CMOS: Circuit Level Approach.- Low-Power Low-Voltage ?-? ADC Design in Nanometer CMOS: System Level Approach.- Conclusions.