The book gives an overview of the state-of-the-art in SigmaDelta design and of the challenges for future realizations. It provides an understanding of the fundamental power efficiency of SigmaDelta converters. In addition, it presents an analysis of the power consumption in the decimation filter. Understanding these power/performance trade-offs, it becomes clear that straight-forward digitization of a conditioning channel, i.e. exchanging analog for digital conditioning, comes at a major power penalty.

1.1 Background Moore's Law predicts a decrease by a factor of two in the feature size of CMOS te- nology every three years and has been valid for years. It implies a doubling of the - eration speed and a four times higher transistor count per unit of area, every three years. The combination leads to an eight times higher processing capability per unit of area. This on-going miniaturization allows the integration of complex electronic systems with millions of transistors (Very-Large-Scale-Integration) and enables the integration of el- tronic systems. An electronic system A generic picture of an integrated electronic system is shown in ?g. 1.1. The heart of the system is the signal processing core. This core supports a wide variety of functions, such as customization and programmability of multiple applications, channel coding, the de?nition of the user interface, etc. These functions are enabled by DSP, a controller CPU and various blocks of memory. In advanced ICs these blocks provide (almost) all signal processing and usually dominate in the overall power and area consumption of integrated systems. The huge data rates involved, require high-speed busses for communication between these blocks. A power-management unit fuels the system by providing the - propriate supply voltages and currents.

Provides an accessible overview of the state-of-the-art in sigma-delta converter design Derives the power/performance relation of both the sigma-delta converter and the decimation filter Analyzes the various aspects of the interferer-immunity of a continuous-time sigma-delta converter Presents advanced sigma-delta topologies with improved interferer-immunity Studies the sigma-delta converter within a receiver application and presents an alternative highly-digital receiver with signal conditioning integrated into the sigma-delta converter

Autorentext

Kathleen Philips was born in 1972, in Aalst, Belgium. In 1992 and in 1995, respectively, she obtained the B. Sc. and the M. Sc. degree in Electrical Engineering from the "Katholieke Universiteit Leuven" in Belgium. The graduation project was on the design of monolithic microwave ICs based on HEMT-transistors.

In the summer of 1993, she did a traineeship at the IMEC, Belgium, on methodologies to evaluate contamination in IC technology steps.

In September 1995, she started working in the Mixed-signal Circuits and Systems group of the Philips Research Laboratories in Eindhoven, the Netherlands, where she is now a senior research scientist. She respectively worked on the design of D/A converters and class-D amplifiers for audio, sigma delta A/D conversion for FM and AMradio, variable-gain amplifiers, sigma delta design for UMTS and for Bluetooth receivers. Her research interests also include the system-level design of transceivers for wireless communication.

In the fall of 1997, she was seconded to Philips Semiconductors, France, on the topic of PLL design. Another secondment in 2000, to the Philips Research Laboratories in the United Kingdom, involved the study of third-generation mobile receivers and the derivation of circuit specifications.

The author was a lecturer in the Educational Sessions of the IEEE Custom Integrated Circuits Conference in 2003 and 2004. From 2005 on, she also serves in the technical program committee of this conference.

Klappentext

1.1 Background Moore s Law predicts a decrease by a factor of two in the feature size of CMOS te- nology every three years and has been valid for years. It implies a doubling of the - eration speed and a four times higher transistor count per unit of area, every three years. The combination leads to an eight times higher processing capability per unit of area. This on-going miniaturization allows the integration of complex electronic systems with millions of transistors (Very-Large-Scale-Integration) and enables the integration of el- tronic systems. An electronic system A generic picture of an integrated electronic system is shown in ?g. 1.1. The heart of the system is the signal processing core. This core supports a wide variety of functions, such as customization and programmability of multiple applications, channel coding, the de?nition of the user interface, etc. These functions are enabled by DSP, a controller CPU and various blocks of memory. In advanced ICs these blocks provide (almost) all signal processing and usually dominate in the overall power and area consumption of integrated systems. The huge data rates involved, require high-speed busses for communication between these blocks. A power-management unit fuels the system by providing the - propriate supply voltages and currents.

Inhalt

List of symbols and abbreviations. 1 Introduction. 2 The signal conditioning channel. 3 SigmaDelta A/D conversion. 4 Power consumption in channel building blocks. 5 Full-analog and full-digital conditioning channels. 6 Conditioning SigmaDelta ADCs. 7 Digitization of the inter-die interface. 8 Highly analog and highly digital channels for FM/AM radio. 9 Conditioning SigmaDelta ADCs for Bluetooth. 10 General conclusions. A. Overview of published SigmaDelta ADCs. B. Power/performance relation of analog circuits. C. Power/performance relation of digital filters. D. Third-order distortion in analog circuits and SigmaDelta ADCs. E. Power consumption in a data interface. References.