Finite State Machine Datapath Design, Optimization, and Implementation explores the design space of combined FSM/Datapath implementations. The lecture starts by examining performance issues in digital systems such as clock skew and its effect on setup and hold time constraints, and the use of pipelining for increasing system clock frequency. This is followed by definitions for latency and throughput, with associated resource tradeoffs explored in detail through the use of dataflow graphs and scheduling tables applied to examples taken from digital signal processing applications. Also, design issues relating to functionality, interfacing, and performance for different types of memories commonly found in ASICs and FPGAs such as FIFOs, single-ports, and dual-ports are examined. Selected design examples are presented in implementation-neutral Verilog code and block diagrams, with associated design files available as downloads for both Altera Quartus and Xilinx Virtex FPGA platforms. A working knowledge of Verilog, logic synthesis, and basic digital design techniques is required. This lecture is suitable as a companion to the synthesis lecture titled Introduction to Logic Synthesis using Verilog HDL. Table of Contents: Calculating Maximum Clock Frequency / Improving Design Performance / Finite State Machine with Datapath (FSMD) Design / Embedded Memory Usage in Finite State Machine with Datapath (FSMD) Designs

Autorentext

Justin Stanford Davis received his Ph.D. in Electrical Engineering from the Georgia Institute of Technology in August 2003, as well as his M.S. and B.E.E. degrees in 1999 and 1997. During the summers of 1998 and 1999, he worked at Hewlett-Packard (now Agilent Technologies). In fall of 2003, he joined the faculty in the Department of Electrical Engineering at Mississippi State University as an Assistant Professor. His research interests include digital testing for high-speed systems, SoCs, and SoPs, as well as signal integrity, systems engineering, and faulttolerant design. He is currently working on the development of low-cost test support processors using programmable devices.

Inhalt
Calculating Maximum Clock Frequency.- Improving Design Performance.- Finite State Machine with Datapath (FSMD) Design.- Embedded Memory Usage in Finite State Machine with Datapath (FSMD) Designs.