At 90 nm, wires account for nearly 75% of the total delay in a circuit. Even more insidious, however, is that among nearly 40% of these nets, more than 50% of their total net capacitance are attributed to the cross-coupling capacitance between neighboring signals. At this point a new design and optimization paradigm based on real wires is required. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure. From a manufacturability standpoint, nanometer routers must explicitly deal with the ever increasing design complexity, and be capable of adapting to the constraint requirements of timing, signal integrity, process antenna effect, and new interconnect architecture such as X-architecture.

In the nanometer era, we must look into new-generation routing technologies that combine high performance and capacity with the integration of congestion, timing, SI prevention, and DFM algorithms as the best means of getting to design closure quickly. In this book, we present a novel multilevel full-chip router, namely mSIGMA for SIGnal-integrity and MAnufacturability optimization. And these routing technologies will ensure faster time-to-market and time-to-profitability.

Describes a full-chip nanometer routing techniques A detailed description on the modern VLSI routing problems Multilevel optimization on routing design to solve the chip complexity problem

Autorentext

Kai Hu received his B. Sci. degree from Fudan University, Shanghai, China, in 2009, and the M.S. and Ph.D. degree from Duke University, NC, USA, in 2011 and 2015, respectively. He was the recipient of the VLSI Test Symposium (VTS) Best Paper Award in 2013, IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award in 2015, and European Design and Automation Association (EDAA) Outstanding Dissertation Award in 2016. He is currently a Senior Engineer with Oracle. Inc., Santa Clara, CA, USA. His current research interests include algorithms for computer-aided design and testing of flow-based microfluidic biochips. Krishnendu Chakrabarty is the William H. Younger Distinguished Professor of Engineering in the Department of Electrical and Computer Engineering, at Duke University in Durham, NC. He has been at Duke University since 1998. His current research is focused on: testing and design-for-testability of integrated circuits (especially 3D and multicore chips); digital microfluidics, biochips, and cyberphysical systems; optimization of digital print and production system infrastructure. His research projects in the recent past have also included chip cooling using digital microfluidics, wireless sensor networks, and real-time embedded systems. Research support is provided by the National Science Foundation, the Semiconductor Research Corporation, Cisco Systems, HP Labs, Huawei Technologies, and Intel Corporation through Intel Lab's Academic Research Office. Other sponsors in the past have included National Institutes of Health , DARPA and the Office of Naval Research. Prof. Chakrabarty received the B. Tech. degree from the Indian Institute of Technology, Kharagpur, India in 1990, and the M.S.E. and Ph.D. degrees from the University of Michigan, Ann Arbor in 1992 and 1995, respectively, all in Computer Science and Engineering . During 1990-95, he was a research assistant at the Advanced Computer Architecture Laboratory of the Department of Electrical Engineering and Computer Science, University of Michigan. During 1995-1998, he was an Assistant Professor of Electrical and Computer Engineering at Boston University. Prof. Chakrabarty is a Fellow of ACM, a Fellow of IEEE, and a Golden Core Member of the IEEE Computer Society. He is also an Invitational Fellow of the Japan Society for the Promotion of Science (JSPS), 2009. He is a recipient of the IEEE Computer Society Meritorious Service Award. Prof. Chakrabarty was a Chair Professor in the School of Software in Tsinghua University, Beijing, China (2009-2013), and a Visiting Chair Professor in Computer Science and Information Engineering at National Cheng Kung University in Taiwan (2012-2013). He has held Visiting Professor positions at University of Tokyo (Japan), Nara Institute of Science and Technology (Japan), and University of Potsdam (Germany), and a Guest Professor position at University of Bremen (Germany). Tsung-Yi Ho received his Ph.D. in Electrical Engineering from National Taiwan University in 2005. He is a Professor with the Department of Computer Science of National Tsing Hua University, Hsinchu, Taiwan. His research interests include design automation and test for microfluidic biochips and nanometer integrated circuits. He has presented 10 tutorials and contributed 10 special sessions in ACM/IEEE conferences, all in design automation for microfluidic biochips. He has been the recipient of the Invitational Fellowship of the Japan Society for the Promotion of Science (JSPS), the Humboldt Research Fellowship by the Alexander von Humboldt Foundation, and the Hans Fischer Fellow by the Institute of Advanced Study of the Technical University of Munich. He was a recipient of the Best Paper Awards at the VLSI Test Symposium (VTS) in 2013 and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems in 2015. He served as a Distinguished Visitor ofthe IEEE Computer Society for 2013-2015, the Chair of the IEEE Computer

Klappentext

As Moore's Law continues unencumbered into the nanometer era, chips are reaching 1000 M gates in size, process geometries have shrunk to 90 nm and below, and engineers have to face compounded design complexity with every new design. These nanometer-scale designs require a new generation of physics-aware and manufacturing-aware routing. At 90 nm and below, there are so many signal-integrity issues that design teams cannot manually correct them all. At 90 nm, wires account for nearly 75% of the total delay in a circuit. Even more insidious, however, is that among nearly 40% of these nets, more than 50% of their total net capacitance are attributed to the cross-coupling capacitance between neighboring signals. At this point a new design and optimization paradigm based on real wires is required. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure. From a manufacturability standpoint, nanometer routers must explicitly deal with the ever increasing design complexity, and be capable of adapting to the constraint requirements of timing, signal integrity, process antenna effect, and new interconnect architecture such as X-architecture.

In the nanometer era, we must look into new-generation routing technologies that combine high performance and capacity with the integration of congestion, timing, SI prevention, and DFM algorithms as the best means of getting to design closure quickly. In this book, we present a novel multilevel full-chip router, namely mSIGMA for SIGnal-integrity and MAnufacturability optimization. And these routing technologies will ensure faster time-to-market and time-to-profitability.

Inhalt
Routing Challenges for Nanometer Technology.- Multilevel Full-Chip Routing Considering Crosstalk And Performance.- Multilevel Full-Chip Routing Considering Antenna Effect Avoidance.- Multilevel Full-Chip Routing For The X-Based Architecture.- Concluding Remarks And Future Work.