This proceedings volume contains the contributions of the speakers who attended the NATO Advanced Research Workshop on "Perspectives, Science and Technologies for Novel Silicon on Insulator Devices" held at the Sanatorium Pushcha OLema, Kyiv, th Ukraine from It" to 15 October 1998. This meeting was the second NATO Silicon on Insulator (SOl) Workshop to be held in st the Ukraine where the first meeting (Gurzuf, Crimea, 1 to 4th November 1994) focussed upon the physical and technical problems to be addressed in order to exploit the advantages of incorporating SOl materials in device and sensor technologies. On this occasion emphasis was placed upon firstly, promoting the use of SOl substrates for a range of novel device and circuit applications and secondly, addressing the economic issues of incorporating SOl processing technologies and device technologies within the framework of the resources available within the laboratories and factories of the Newly Independent States (NIS). The primary goal of both workshops has been the breaking of the barriers that inhibit closer collaboration between scientists and engineers in the NATO countries and the NIS. Indeed, it was a pleasure for attendees at the first meeting to renew acquaintances and for the first time attendees to make new contacts and enjoy the warm hospitality offered by our hosts in Kyiv. An outcome was the forging of new links and concrete proposals for future collaborations.

Zusammenfassung
Proceedings of the NATO Advanced Research Workshop, Kiev, Ukraine, 12-15 October 1998

Inhalt
Section 1: Innovations in Materials Technologies.- 1.1 Invited SMART-CUT® Technology: Basic Mechanisms and Applications.- 1.2 Invited Polish Stop Technology for Silicon on Silicide on Insulator Structures.- 1.3 Invited Homoepitaxy on Porous Silicon with a Buried Oxide Layer: Full-Wafer Scale SOI.- 1.4 Structural and Electrical Properties of Silicon on Isolator Structures Manufactured on FZ- and CZ-Silicon by SMART-CUT Technology.- 1.5 Development of Linear Sequential Lateral Solidification Technique to Fabricate Quasi-Single-Crystal Super-Thin Si Films for High-Performance Thin Film Transistor Devices.- Section 2: Economics and Innovation Applications.- 2.1 Invited Low Temperature Polysilicon Technology: A Low Cost SOI Technology?.- 2.2 Invited A Novel Low Cost Process for the Production of Semiconductor Polycrystalline Silicon from Recycled Industrial Waste.- 2.3 Invited Tetrahedrally Bonded Amorphous Carbon for Electronic Applications.- 2.4 Invited Diamond Based Silicon-on-Insulator Materials and Devices.- 2.5 Invited Low-Temperature Processing of Crystalline Si Films on Glass for Electronic Applications.- 2.6?-SiC on SiO2 Fonned by Ion Implantation and Bonding for Micromechanics Applications.- 2.7 Laser Recrystallised Polysilicon Layers for Sensor Applications: Electrical and Piezoelectric Characterisation.- Section 3: Characterisation Methods for SOI.- 3.1 Invited Optical Spectroscopy of SOI Materials.- 3.2 Invited Computer Simulation of Oxygen Redistribution in SOI Structures.- 3.3 Invited Electrical Instabilities in Silicon-on-Insulator Structures and Devices During Voltage and Temperature Stressing.- 3.4 Hydrogen as a Diagnostic Tool in Analysing SOI Structures.- 3.5Back Gate Voltage Influence on the LDD SOI NMOSFET Series Resistance Extraction from 150 to 300 K.- 3.6 Characterisation of Porous Silicon Layers Containing a Buried Oxide Layer.- 3.7 Total-Dose Radiation Response of Multilayer Buried Insulators.- 3.8 Recombination Current in Fully-Depleted SOI Diodes: Compact Model and Lifetime Extraction.- 3.9 Investigation of the Structural and Chemical Properties of SOI Materials by Ellipsometry.- 3.10 Experimental Investigation and Modelling of Coplanar Transmission Lines on SOI Technologies for RF Applications.- Section 4: Perspectives for SOI Structures and Devices.- 4.1 Invited Perspectives of Silicon-on-Insulator Technologies for Cryogenic Electronics.- 4.2 Invited SOI CMOS for High-Temperature Applications.- 4.3 Invited Quantum Effect Devices on SOI Substrates with an Ultrathin Silicon Layer.- 4.4 Invited Wafer Bonding for Micro-ElectroMechanical Systems (MEMS).- 4.5 A Comprehensive Analysis of the High-Temperature Off-State and Subthreshold Characteristics of SOI MOSFETs.- 4.6 Influence of Silicon Film Parameters on C-V Characteristics of Partially Depleted SOI MOSFETs.- 4.7 Effect of Shallow Oxide Traps on the Low-Temperature Operation of SOI Transistors.- 4.8 Nanoscale Wave-Ordered Structures on SOI.- 4.9 Thin Partial SOI Power Devices for High Voltage Integrated Circuits.- Keyword Index.- Author Index.