This volumecontains the proceedingsof the Second InternationalConferenceon Formal Methods in Computer-Aided Design (FMCAD 98), organized November 4-6, in Palo Alto, California, USA. The rst event of this series was organized byMandayamSrivasand Albert Camilleriin 1996 inPaloAlto. FMCAD,which evolved from the series Theorem Provers in Circuit Design (TPCD), strives to beapremierforumfordisseminatingresearchinFormalVeri cation(FV) me- ods for digital circuits and systems, including processors, custom VLSI circuits, microcode,andreactivesoftware.Inadditiontosigni cantcase-studiesandve- cationapproaches,FMCADalsoendeavorstorepresentadvancesinthedriving technologies for veri cation, including binary decision diagrams, model che- ing,symbolicreasoning(theorem proving),symbolicsimulation,andabstraction methods. Theconferenceincludedfourinvitedlectures.Theinvitedlecturesweregiven by Kenneth McMillan (Cadence Berkeley Labs) on Minimalist proof assistants: interactions of technology and methodology in formal system level veric ation , by Carl-Johan Seger on Formal methods in CAD from an industrial perspective, by Randal E. Bryant and Bwolen Yang on A performance study of BDD-based model checking, and by Amir Pnueli on Veric ation of data-insensitive circuits: an in-order-retirement case study. Of the 55 regular paper submissionsreceived, 27 were selected by the technical program committee for presentation at the conference. All four tools papers received were also selected. We gratefully acknowledge the services of the technical program comm- tee of FMCAD 98, which consisted of Adnan Aziz (Univ. of Texas at Austin, USA),AlanHu(Univ.ofBritishColumbia,Canada),Albert Camilleri(Hewlett- Packard,USA), CarlPixley(Motorola,USA), CarlosDelgadoKloos (Univ. C- los III de Madrid,Spain), Ching-TsunChou (Intel, USA), EduardCerny (Univ.

Includes supplementary material: sn.pub/extras

Inhalt
Minimalist Proof Assistants: Interactions of Technology and Methodology in Formal System Level Verification.- Reducing Manual Abstraction in Formal Verification of Out- of- Order Execution.- Bit-Level Abstraction in the Verification of Pipelined Microprocessors by Correspondence Checking.- Solving Bit-Vector Equations.- The Formal Design of 1M-Gate ASICs.- Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations.- A Tutorial on Stålmarck's Proof Procedure for Propositional Logic.- Almana: A BDD Minimization Tool Integrating Heuristic and RewritingMethods.- Bisimulation Minimization in an Automata-Theoretic Verification Framework.- Automatic Verification of Mixed-Level Logic Circuits.- A Timed Automaton-Based Method for Accurate Computation of Circuit Delay in the Presence of Cross-Talk.- Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints.- Using MTBDDs for Composition and Model Checking of Real-Time Systems.- Formal Methods in CAD from an Industrial Perspective.- A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool.- Combined Formal Post- and Presynthesis Verification in High Level Synthesis.- Formalization and Proof of a Solution to the PCI 2.1 Bus Transaction Ordering Problem.- A Performance Study of BDD-Based Model Checking.- Symbolic Model Checking Visualization.- Input Elimination and Abstraction in Model Checking.- Symbolic Simulation of the JEM1 Microprocessor.- Symbolic Simulation: An ACL2 Approach.- Verification of Data-Insensitive Circuits: An In-Order-Retirement Case Study.- Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification.- Formally Verifying Data and Controlwith Weak Reachability Invariants.- Generalized Reversible Rules.- An Assume-Guarantee Rule for Checking Simulation.- Three Approaches to Hardware Verification: HOL, MDG, and VIS Compared.- An Instruction Set Process Calculus.- Techniques for Implicit State Enumeration of EFSMs.- Model Checking on Product Structures.- BDDNOW: A Parallel BDD Package.- Model Checking VHDL with CV.- Alexandria: A Tool for Hierarchical Verification.- PV: An Explicit Enumeration Model-Checker.