Adaptive Techniques for Mixed Signal Sytem on Chip discusses the concept of adaptation in the context of analog and mixed signal design along with different adaptive architectures used to control any system parameter. The first part of the book gives an overview of the different elements that are normally used in adaptive designs including tunable elements as well as voltage, current, and time references with an emphasis on the circuit design of specific blocks such as voltage-controlled transconductors, offset comparators, and a novel technique for accurate implementation of on chip resistors. While the first part of the book addresses adaptive techniques at the circuit and block levels, the second part discusses adaptive equalization architectures employed to minimize the impact of ISI (Intersymbol Interference) on the quality of received data in high-speed wire line transceivers. It presents the implementation of a 125Mbps transceiver operating over a variable length of Category 5 (CAT-5) Ethernet cable as an example of adaptive equalizers.

Emphasizes design techniques in low-voltage, deep sub-micron digital processes towards better yield Devoted to adaptive techniques in mixed signal designs to achieve first-pass silicon Principles presented are generic and apply to many mixed signal CMOS SoC solutions Theory presented is validated and demonstrated through real industrial applications Design techniques presented will significantly help improve the yield of mixed signal SoCs Includes supplementary material: sn.pub/extras

Klappentext

Adaptive Techniques for Mixed Signal Sytem on Chip discusses the concept of adaptation in the context of analog and mixed signal design along with different adaptive architectures used to control any system parameter. The first part of the book gives an overview of the different elements that are normally used in adaptive designs including tunable elements as well as voltage, current, and time references with an emphasis on the circuit design of specific blocks such as voltage-controlled transconductors, offset comparators, and a novel technique for accurate implementation of on chip resistors. While the first part of the book addresses adaptive techniques at the circuit and block levels, the second part discusses adaptive equalization architectures employed to minimize the impact of ISI (Intersymbol Interference) on the quality of received data in high-speed wire line transceivers. It presents the implementation of a 125Mbps transceiver operating over a variable length of Category 5 (CAT-5) Ethernet cable as an example of adaptive equalizers.

Inhalt
Adaptive Architectures.- Tunable Elements.- On-Chip Resistors and Capacitors.- A Digital Adaptive Technique for On-Chip Resistors.- Equalization.- An Analog Adaptive Equalizer for Wire Line Transceivers.