TheARCSseriesofconferenceshasover30yearsoftraditionreportingtop-notch results in computer architecture and operating systems research. It is organized by the special interest group on Computer and System Architecture of the GI (Gesellschaft fur Informatik e.V.) and ITG (Informationstechnische Gesellschaft imVDE InformationTechnologySociety).In2010,ARCSwashostedbyLeibniz University Hannover. This year s special focus was on heterogeneous systems. The conference s topics comprised design aspects of multi-cores and memory systems, adaptive system architectures such as recon?gurable systems in hardware and software, customization and application-speci?c accelerators in heterogeneous archit- tures, organic and autonomic computing, energy-awareness, system aspects of ubiquitous and pervasive computing, and embedded systems. Thecallforpapersattractedabout55submissionsfromallaroundtheworld. Each submission was assigned to at least three members of the Program C- mittee for review. The Program Committee decided to accept 20 papers, which were arranged in seven sessions. The accepted papers are from Belgium, China, France, Germany, Italy, Spain, Turkey, and the UK. Two keynotes on hetero- neous systems complemented the strong technical program.

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Autorentext
Prof. Dr. Wolfgang Karl ist seit 2003 Professor für Entwurf von Systemen in Hardware / Organisation Innovativer Rechnerstrukturen am Institut für Technische Informatik der Universität Karlsruhe (TH).
Der Schwerpunkt seiner wissenschaftlichen Interessen liegt auf dem Gebiet der Rechnerarchitektur, insbesondere dem Entwurf und der Organisation paralleler Systeme, ihrer Programmierung und ihrer Werkzeuge, Prozessorarchitekturen sowie dem Entwurf eingebetteter Systeme. Wolfgang Karl ist Autor von über 80 Fachpublikationen, darunter Monographien und Veröffentlichungen in Buchreihen und wissenschaftlichen Zeitschriften

Inhalt
Keynote.- HyVM - Hybrid Virtual Machines - Efficient Use of Future Heterogeneous Chip Multiprocessors.- Processor Design.- How to Enhance a Superscalar Processor to Provide Hard Real-Time Capable In-Order SMT.- Complexity-Effective Rename Table Design for Rapid Speculation Recovery.- An Embedded GC Module with Support for Multiple Mutators and Weak References.- Embedded Systems.- A Hierarchical Distributed Control for Power and Performances Optimization of Embedded Systems.- Autonomic Workload Management for Multi-core Processor Systems.- Firefly Flashing Synchronization as Inspiration for Self-synchronization of Walking Robot Gait Patterns Using a Decentralized Robot Control Architecture.- Organic Computing and Self-organization.- The JoSchKa System: Organic Job Distribution in Heterogeneous and Unreliable Environments.- On Deadlocks and Fairness in Self-organizing Resource-Flow Systems.- Ad-Hoc Information Spread between Mobile Devices: A Case Study in Analytical Modeling of Controlled Self-organization in IT Systems.- Processor Design and Transactional Memory.- MLP-Aware Instruction Queue Resizing: The Key to Power-Efficient Performance.- Exploiting Inactive Rename Slots for Detecting Soft Errors.- Efficient Transaction Nesting in Hardware Transactional Memory.- Energy Management in Distributed Environments and Ad-Hoc Grids.- Decentralized Energy-Management to Control Smart-Home Architectures.- EnergySaving Cluster Roll: Power Saving System for Clusters.- Effect of the Degree of Neighborhood on Resource Discovery in Ad Hoc Grids.- Performance Modelling and Benchmarking.- Compiler-Directed Performance Model Construction for Parallel Programs.- A Method for Accurate High-Level Performance Evaluation of MPSoC Architectures Using Fine-Grained Generated Traces.- JetBench:An Open Source Real-time Multiprocessor Benchmark.- Accelerators and GPUs.- A Tightly Coupled Accelerator Infrastructure for Exact Arithmetics.- Optimizing Stencil Application on Multi-thread GPU Architecture Using Stream Programming Model.