This book walks the reader through the next step in the evolution of NAND flash memory technology, namely the development of 3D flash memories, in which multiple layers of memory cells are grown within the same piece of silicon. It describes their working principles, device architectures, fabrication techniques and practical implementations, and highlights why 3D flash is a brand new technology.

After reviewing market trends for both NAND and solid state drives (SSDs), the book digs into the details of the flash memory cell itself, covering both floating gate and emerging charge trap technologies. There is a plethora of different materials and vertical integration schemes out there. New memory cells, new materials, new architectures (3D Stacked, BiCS and P-BiCS, 3D FG, 3D VG, 3D advanced architectures); basically, each NAND manufacturer has its own solution. Chapter 3 to chapter 7 offer a broad overview of how 3D can materialize. The 3D wave is impacting emerging memories as well and chapter 8 covers 3D RRAM (resistive RAM) crosspoint arrays. Visualizing 3D structures can be a challenge for the human brain: this is way all these chapters contain a lot of bird's-eye views and cross sections along the 3 axes.

The second part of the book is devoted to other important aspects, such as advanced packaging technology (i.e. TSV in chapter 9) and error correction codes, which have been leveraged to improve flash reliability for decades. Chapter 10 describes the evolution from legacy BCH to the most recent LDPC codes, while chapter 11 deals with some of the most recent advancements in the ECC field. Last but not least, chapter 12 looks at 3D flash memories from a system perspective.

Is 14nm the last step for planar cells? Can 100 layers be integrated within the same piece of silicon? Is 4 bit/cell possible with 3D? Will 3D be reliable enough for enterprise and datacenter applications? These are some of the questions that this book helps answering by providing insights into 3D flash memory design, process technology and applications.

The first book to focus on 3D flash memories Provides details of flash 3D architectures which have never been published before, including a number of 3D cross sections Offers unique coverage of flash with Through-Silicon-Via (TSV) technology Includes supplementary material: sn.pub/extras

Autorentext
Dr. Rino Micheloni is Fellow at Microsemi Corporation where he currently runs the Non-Volatile Memory Lab in Milan, with special focus on NAND Flash. Prior to joining Microsemi, he was Fellow at PMC-Sierra, working on NAND Flash characterization, LDPC, and NAND Signal Processing as part of the team developing Flash controllers for PCIe SSDs. Before that, he was with IDT (Integrated Device Technology) as Lead Flash Technologist, driving the architecture and design of the BCH engine in the world's 1st PCIe NVMe SSD controller. Early in his career, he led Flash design teams at STMicroelectronics, Hynix, Infineon, and Qimonda; during this time, he developed the industry's first MLC NOR device with embedded ECC technology and the industry's first MLC NAND with embedded BCH. Rino is IEEE Senior Member, he has co-authored more than 50 publications, and he holds 240 patents worldwide (including 118 US patents). He received the STMicroelectronics Exceptional Patent Award in 2003 and2004, and the Qimonda IP Award in 2007. Rino has published the following books with Springer: Inside Solid State Drives (2013), Inside NAND Flash Memories (2010), Error Correction Codes for Non-Volatile Memories (2008), Memories in Wireless Systems (2008), and VLSI-Design of Non-Volatile Memories (2005).

Inhalt

Dedication Page.- Foreword.- Preface.- Introduction.- About the Editor.- Acknowledgements.- 1 The Business of NAND.- 2 Reliability of 3D NAND Flash memories.- 3 3D Stacked NAND Flash memories.- 4 3D Charge Trap NAND Flash memories.- 5 3D Floating Gate NAND Flash memories.- 6 Advanced Architectures for 3D NAND Flash memories with vertical channel.- 7 3D VG-Type NAND Flash memories.- 8 RRAM Cross-point arrays.- 9 3D Multi-Chip Integration and Packaging Technology.- 10 BCH and LDPC Error Correction Codes for NAND Flash memories.- 11 Advanced algebraic and graph-based ECC schemes for modern NVMs.- 12 System-Level Considerations on Design of 3D NAND Flash memories.- Index.