VLSI-SoC: Advanced Topics on Systems on a Chip

International Federation for Information Processing

The IFIP series publishes state-of-the-art results in the sciences and technologies of information and communication. The scope of the series includes: foundations of computer science; software theory and practice; education; computer applications in technology; communication systems; systems modeling and optimization; information systems; computers and society; computer systems technology; security and protection in information processing systems; artificial intelligence; and human-computer interaction. Proceedings and post-proceedings of refereed international conferences in computer science and interdisciplinary fields are featured. These results often precede journal publication and represent the most current research. The principal aim of the IFIP series is to encourage education and the dissemination and exchange of information about all aspects of computing.

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Inhalt

Statistical Analysis of Normality of Systematic and Random Variability of Flip-Flop Race Immunity in 130nm and 90nm CMOS Technologies..- Use of Gray Decoding for Implementation of Symmetric Functions.- A Programmable Multi-Dimensional Analog Radial-Basis- Function-Based Classifier.- Compression-based SoC Test Infrastructures.- Parametric Structure-Preserving Model Order Reduction.- ReCPU: a Parallel and Pipelined Architecture for Regular Expression Matching.- QoS in Networks-on-Chip - Beyond Priority and Circuit Switching Techniques.- Accurate Performance Estimation using Circuit Matrix Models in Analog Circuit Synthesis.- Statistical and Numerical Approach for a Computer efficient circuit yield analysis.- SWORD: A SAT like Prover Using Word Level Information.- A new analytical approach of the impact of jitter on continuous time delta sigma converters..- An adaptive genetic algorithm for dynamically reconfigurable modules allocation.- The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm.- System and Procesor Design Effort Estimation.- Reconfigurable Acceleration with Binary Compatibility for General Purpose Processors.- First Order, Quasi-Static, SOI Charge Conserving Power Dissipation Model.