Here is an accessible, comprehensive guide to all the popular modern RISC (Reduced Instruction Set Computer) processors: MIPS, SPARC, PowerPC, ARM and Itanium. It details RISC design principles as well as explains the differences between RISC and CISC designs. It also covers MIPS assembly language programming. Professionals and programmers seeking an authoritative and practical overview of RISC processors will find the guide an essential resource.

Klappentext

Recently, there has been a trend toward processor design based on the RISC (Reduced Instruction Set Computer) model: Example RISC processors are the MIPS, SPARC, PowerPC, ARM, and even Intel's 64-bit processor Itanium.

This guidebook provides an accessible and all-encompassing compendium on RISC processors, introducing five RISC processors: MIPS, SPARC, PowerPC, ARM, and Itanium. Initial chapters explain the differences between the CISC and RISC designs and clearly discuss the core RISC design principles. The text then integrates instruction on MIPS assembly language programming, thereby enabling readers to concretely grasp concepts and principles introduced earlier. Readers need only have a basic knowledge of any structured, high-level language to obtain the full benefits here.

Features:

*Includes MIPS simulator (SPIM) download instructions, so that readers can get hands-on assembly language programming experience

*Presents material in a manner suitable for flexible self-study

• Assembly language programs permit reader executables using the SPIM simulator

• Integrates core concepts to processor designs and their implementations

• Supplies extensive and complete programming examples and figures

• Contains chapter-by-chapter overviews and summaries

• Provides source code for the MIPS language at the book's website

Guide to RISC Processors* provides a uniquely comprehensive introduction and guide to RISC-related concepts, principles, design philosophy, and actual programming, as well as the all the popular modern RISC processors and their assembly language. Professionals, programmers, and students seeking an authoritative and practical overview of RISC processors and assembly language programming will find the guide an essential resource.

Sivarama P. Dandamudi is a professor of computer science at Carleton University inOttawa, Ontario, Canada, as well as associate editor responsible for computer architecture at the International Journal of Computers and Their Applications. He has more than two decades of experience teaching about computer systems and organization. 

Key Topics

• Processor design issues

• Evolution of CISC and RISC processors

• MIPS, SPARC, PowerPC, Itanium, and ARM architectures

• MIPS assembly language

• SPIM simulator and debugger

• Conditional execution

• Floating-point and logical and shift operations

• Number systems

Computer Architecture/Programming

Beginning/Intermediate Level

Zusammenfassung

Recently, there has been a trend toward processors based on the RISC (Reduced Instruction Set Computer) design. This is an accessible and all-encompassing compendium on RISC processors, introducing five of them: MIPS, SPARC, PowerPC, ARM, and Intel's 64-bit Itanium. Initial chapters explain differences between the CISC and RISC designs, and the core RISC design principles are clearly discussed. Later chapters provide instruction on MIPS assembly language programming, so that readers can readily learn the concepts and principles introduced earlier. Professionals, programmers, and students in computer architecture and programming courses will find the guide an essential resource.

Inhalt
Overview.- Processor Design Issues.- RISC Principles.- Architectures.- MIPS Architecture.- SPARC Architecture.- PowerPC Architecture.- Itanium Architecture.- ARM Architecture.- MIPS Assembly Language.- SPIM Simulator and Debugger.- Assembly Language Overview.- Procedures and the Stack.- Addressing Modes.- Arithmetic Instructions.- Conditional Execution.- Logical and Shift Operations.- Recursion.- Floating-Point Operations.