It is universally accepted today that parallel processing is here to stay but that software for parallel machines is still difficult to develop. However, there is little recognition of the fact that changes in processor architecture can significantly ease the development of software. In the seventies the availability of processors that could address a large name space directly, eliminated the problem of name management at one level and paved the way for the routine development of large programs. Similarly, today, processor architectures that can facilitate cheap synchronization and provide a global address space can simplify compiler development for parallel machines. If the cost of synchronization remains high, the pro­ gramming of parallel machines will remain significantly less abstract than programming sequential machines. In this monograph Bob Iannucci presents the design and analysis of an architecture that can be a better building block for parallel machines than any von Neumann processor. There is another very interesting motivation behind this work. It is rooted in the long and venerable history of dataflow graphs as a formalism for ex­ pressing parallel computation. The field has bloomed since 1974, when Dennis and Misunas proposed a truly novel architecture using dataflow graphs as the parallel machine language. The novelty and elegance of dataflow architectures has, however, also kept us from asking the real question: "What can dataflow architectures buy us that von Neumann ar­ chitectures can't?" In the following I explain in a round about way how Bob and I arrived at this question.

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One: The Problem Domain.- 1.1 Abstract Program Representation.- The WaveFront Example.- Expressions.- Loops.- Data Types.- 1.2 Two Fundamental Issues.- Latency: The First Fundamental Issue.- Synchronization: The Second Fundamental Issue.- 1.3 The Cost of Parallelism.- Assumptions.- Analysis.- 1.4 Summary.- Two: The Importance of Processor Architecture.- 2.1 von Neumann Architectures.- Tolerating Latency.- Synchronization Methods.- Analysis and Summary.- 2.2 Dataflow Architectures.- 2.3 Comparison of Approaches.- 2.4 Summary.- Three: A Dataflow / von Neumann Hybrid.- 3.1 Synthesis.- 3.2 Compilation Target Model.- A Suitable Program Representation.- Support for Synchronization.- Latency.- Overview of the Model.- 3.3 Execution Models.- The Ideal Processor.- The Realistic Processor.- 3.4 Summary.- Four: Compiling for the Hybrid Architecture.- 4.1 DFPG Revisited.- DFPG Instructions.- Codeblocks.- 4.2 Strategic Issues for Partitioning.- Possible Constraints.- Scope.- Examples.- Latency-Directed Partitioning.- Summary.- 4.3 Code Generator.- Overall Goal and Method.- Simplifications.- Partitioning Constraints.- Operand Storage Allocation.- Machine Code Generation and Partitioning.- Optimizer.- Assembler.- 4.4 Summary.- Five: Analysis.- 5.1 Idealized Model.- Static Statistics.- Dynamic Characteristics.- WaveFront Revisited.- Power of a Hybrid Instruction.- 5.2 Realistic Model.- Cache Operating Point.- Cache Robustness.- Parallelism.- Toleration of Latency.- 5.3 Summary.- Six: Conclusion.- 6.1 Summary of the Present Work.- 6.2 Future Work.- 6.3 Related Work.- HEP Revisited.- MASA Revisited.- The UCI Process-Oriented Model Project.- The IBM/ETH Project.- 6.4 Closing Remarks.- References.