Design of High-Performance CMOS Voltage-Controlled Oscillators presents a phase noise modeling framework for CMOS ring oscillators. The analysis considers both linear and nonlinear operation. It indicates that fast rail-to-rail switching has to be achieved to minimize phase noise. Additionally, in conventional design the flicker noise in the bias circuit can potentially dominate the phase noise at low offset frequencies. Therefore, for narrow bandwidth PLLs, noise up conversion for the bias circuits should be minimized. We define the effective Q factor (Qeff) for ring oscillators and predict its increase for CMOS processes with smaller feature sizes. Our phase noise analysis is validated via simulation and measurement results.
The digital switching noise coupled through the power supply and substrate is usually the dominant source of clock jitter. Improving the supply and substrate noise immunity of a PLL is a challenging job in hostile environments such as a microprocessor chip where millions of digital gates are present.

Inhalt

List of Figures. List of Tables. Preface. Acknowledgments. 1. Introduction. 2. Introduction to PLLS. 3. Phase Noise and Timing Jitter. 4. Review of Existing VCO Phase Noise Models. 5. Universal Model for Ring Oscillator Phase Noise. 6. New Ring VCO Design. 7. PLL Design Examples. 8. Conclusions. Index.