Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Welcome to the proceedings of PATMOS 2005, the 15th in a series of international workshops.PATMOS2005wasorganizedbyIMECwithtechnicalco-sponsorshipfrom the IEEE Circuits and Systems Society. Over the years, PATMOS has evolved into an important European event, where - searchers from both industry and academia discuss and investigate the emerging ch- lenges in future and contemporary applications, design methodologies, and tools - quired for the developmentof upcominggenerationsof integrated circuits and systems. The technical program of PATMOS 2005 contained state-of-the-art technical contri- tions, three invited talks, a special session on hearing-aid design, and an embedded - torial. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on modeling, design, char- terization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert revi- ers, selected the 74 papers to be presented at PATMOS. The papers were divided into 11 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, the review process was anonymous, full papers were required, and several reviews were carried out per paper. Beyond the presentations of the papers, the PATMOS technical program was - riched by a series of speeches offered by world class experts, on important emerging research issues of industrial relevance. Prof. Jan Rabaey, Berkeley, USA, gave a talk on "Traveling the Wild Frontier of Ulta Low-Power Design", Dr. Sung Bae Park, S- sung, gave a presentation on "DVL (Deep Low Voltage): Circuits and Devices", Prof.

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Session 1: Low-Power Processors.- A Power-Efficient and Scalable Load-Store Queue Design.- Power Consumption Reduction Using Dynamic Control of Micro Processor Performance.- Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications.- Dynamic Instruction Cascading on GALS Microprocessors.- Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width.- Session 2: Code Optimization for Low-Power.- A Retargetable Environment for Power-Aware Code Evaluation: An Approach Based on Coloured Petri Net.- Designing Low-Power Embedded Software for Mass-Produced Microprocessor by Using a Loop Table in On-Chip Memory.- Energy Characterization of Garbage Collectors for Dynamic Applications on Embedded Systems.- Optimizing the Configuration of Dynamic Voltage Scaling Points in Real-Time Applications.- Session 3: High-Level Design.- Systematic Preprocessing of Data Dependent Constructs for Embedded Systems.- Temperature Aware Datapath Scheduling.- Memory Hierarchy Energy Cost of a Direct Filtering Implementation of the Wavelet Transform.- Improving the Memory Bandwidth Utilization Using Loop Transformations.- Power-Aware Scheduling for Hard Real-Time Embedded Systems Using Voltage-Scaling Enabled Architectures.- Session 4: Telecommunications and Signal Processing.- Design of Digital Filters for Low Power Applications Using Integer Quadratic Programming.- A High Level Constant Coefficient Multiplier Power Model for Power Estimation on High Levels of Abstraction.- An Energy-Tree Based Routing Algorithm in Wireless Ad-Hoc Network Environments.- Energy-Aware System-on-Chip for 5 GHz Wireless LANs.- Low-Power VLSI Architectures for OFDM Transmitters Based on PAPR Reduction.- Session 5: Low-Power Circuits.- An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits.- Power Management for Low-Power Battery Operated Portable Systems Using Current-Mode Techniques.- Power Consumption in Reversible Logic Addressed by a Ramp Voltage.- Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for Vth Assignment and Path Balancing.- Back Annotation in High Speed Asynchronous Design.- Session 6: System-on-Chip Design.- Optimization of Reliability and Power Consumption in Systems on a Chip.- Performance Gains from Partitioning Embedded Applications in Processor-FPGA SoCs.- A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design.- Power Supply Selective Mapping for Accurate Timing Analysis.- Session 7: Busses and Interconnections.- Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses.- PSK Signalling on NoC Buses.- Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding.- Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing.- Efficient Simulation of Power/Ground Networks with Package and Vias.- Session 8: Modeling.- Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation.- Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates.- Compact Static Power Model of Complex CMOS Gates.- Energy Consumption in RC Tree Circuits with Exponential Inputs: An Analytical Model.- Statistical Critical Path Analysis Considering Correlations.- Session 9: Design Automation.- A CAD Platform for Sensor Interfaces in Low-Power Applications.- An Integrated Environment for Embedded Hard Real-Time Systems Scheduling with Timing and Energy Constraints.- Efficient Post-layout Power-Delay Curve Generation.- Power - Performance Optimization for Custom Digital Circuits.- Switching-Activity Directed Clustering Algorithm for Low Net-Power Implementation of FPGAs.- Session 10: Low-Power Techniques.- Logic-Level Fast Current Simulation for Digital CMOS Circuits.- Design of Variable Input Delay Gates for Low Dynamic Power Circuits.- Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications.- Power Dissipation Reduction During Synthesis of Two-Level Logic Based on Probability of Input Vectors Changes.- Session 11: Memory and Register Files.- Energy-Efficient Value-Based Selective Refresh for Embedded DRAMs.- Design and Implementation of a Memory Generator for Low-Energy Application-Specific Block-Enabled SRAMs.- Static Noise Margin Analysis of Sub-threshold SRAM Cells in Deep Sub-micron Technology.- An Adaptive Technique for Reducing Leakage and Dynamic Power in Register Files and Reorder Buffers.- Parameter Variation Effects on Timing Characteristics of High Performance Clocked Registers.- Poster Session 1: Applications.- Low-Power Aspects of Nonlinear Signal Processing.- Reducing Energy Consumption of Computer Display by Camera-Based User Monitoring.- Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives.- A Design Methodology for Secured ICs Using Dynamic Current Mode Logic.- Power Consumption Characterisation of the Texas Instruments TMS320VC5510 DSP.- A Method to Design Compact Dual-rail Asynchronous Primitives.- Enhanced GALS Techniques for Datapath Applications.- Optimizing SHA-1 Hash Function for High Throughput with a Partial Unrolling Study.- Poster Session 2: Digital Circuits.- Area-Aware Pipeline Gating for Embedded Processors.- Fast Low-Power 64-Bit Modular Hybrid Adder.- Speed Indicators for Circuit Optimization.- Synthesis of Hybrid CBL/CMOS Cell Using Multiobjective Evolutionary Algorithms.- Power-Clock Gating in Adiabatic Logic Circuits.- The Design of an Asynchronous Carry-Lookahead Adder Based on Data Characteristics.- Efficient Clock Distribution Scheme for VLSI RNS-Enabled Controllers.- Power Dissipation Impact of the Technology Mapping Synthesis on Look-Up Table Architectures.- Poster Session 3: Analog and Physical Design.- The Optimal Wire Order for Low Power CMOS.- Effect of Post-oxidation Annealing on the Electrical Properties of Anodic Oxidized Films in Pure Water.- Temperature Dependency in UDSM Process.- Circuit Design Techniques for On-Chip Power Supply Noise Monitoring System.- A Novel Approach to the Design of a Linearized Widely Tunable Very Low Power and Low Noise Differential Transconductor.- A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers.- Spec…