VLSI Specification, Verification and Synthesis

VLSI Specification, Verification and Synthesis Proceedings of a workshop held in Calgary from 12-16 January 1987. The collection of papers in this book represents some of the discussions and presentations at a workshop on hardware verification held in Calgary, January 12-16 1987. The thrust of the workshop was to give the floor to a few leading researchers involved in the use of formal approaches to VLSI design, and provide them ample time to develop not only their latest ideas but also the evolution of these ideas. In contrast to simulation, where the objective is to assist in detecting errors in system behavior in the case of some selected inputs, the intent of hardware verification is to formally prove that a chip design meets a specification of its intended behavior (for all acceptable inputs). There are several important applications where formal verification of designs may be argued to be cost-effective. Examples include hardware components used in "safety critical" applications such as flight control, industrial plants, and medical life-support systems (such as pacemakers). The problems are of such magnitude in certain defense applications that the UK Ministry of Defense feels it cannot rely on commercial chips and has embarked on a program of producing formally verified chips to its own specification. Hospital, civil aviation, and transport boards in the UK will also use these chips. A second application domain for verification is afforded by industry where specific chips may be used in high volume or be remotely placed.

Contenu

1 Implementing Safety Critical Systems: The VIPER Microprocessor.- 2 A Proof of Correctness of the VIPER Microprocessors: The First Level.- 3 HOL: A Proof Generating System for Higher-Order Logic.- 4 Formal Verification and Implementation of a Microprocessor.- 5 Toward a Framework for Dealing with System Timing in Very High Level Silicon Compilers.- 6 BIDS: A Method for Specifying Bidirectional Hardware Devices.- 7 Hardware Verification in the Interactive VHDL Workstation.- 8 Contextual Constraints for Design and Verification.- 9 Abstraction Mechanisms for Hardware Verification.- 10 Formal Validation of an Integrated Circuit Design Style.- 11 A Compositional Model of MOS Circuits.- 12 A Tactical Framework for Hardware Design.- 13 Verification of Asynchronous Circuits: Behaviors, Constraints, and Specifications.