Simultaneous Switching Noise of CMOS Devices and Systems

This monograph presents our recent research on Simultaneous Switching Noise (SSN) and related issues for CMOS based systems. Although some SSN related work was previously reported in the literature, it were mainly for Emitter Coupled Logic (ECL) gates using Bipolar Junction Transistors (BJTs). This present work covers in-depth analysis on estimating SSN and its impact for CMOS based devices and systems. At present semiconductor industries are moving towards scaled CMOS devices and reduced supply voltage. SSN together with coupled noise may limit the packing density, and thereby the frequency of operation of packaged systems. Our goal is to provide efficient and yet reliable methodologies and algorithms to estimate the overall noise containment in single chip and multi-chip package assemblies. We hope that the techniques and results described in this book will be useful as guides for design, package, and system engineers and academia working in this area. Through this monograph, we hope that we have shown the necessity of interactions that are essential between chip design, system design and package design engineers to design and manufacture optimal packaged systems. Work reported in this monograph was partially supported by the grant from Semiconductor Research Corporation (SRC Contract No. 92-MP-086).

Contenu

List of Figures. List of Tables. 1. Introduction. 2. Packages/Scaled CMOS Devices. 3. Methods of Calculating Simultaneous Switching Noise (SSN). 4. Power Distribution Inductance Modeling. 5. Signal Conductors over a Perforated Reference Plane. 6. Dynamic Noise Immunity, and Skewing/Damping SSN Waveform. 7. Application Specific Output Drivers to Reduce SSN. 8. SSN Simulator Architecture. 9. Signal Conductors over a Noisy Reference Plane. 10. Conclusions. 11. Discussion and Future Work. Appendices. References. Index.