Gallium Arsenide Digital Circuits

Gallium Arsenide technology has come of age. GaAs integrated circuits are available today as gate arrays with an operating speed in excess of one Gigabits per second. Special purpose GaAs circuits are used in optical fiber digital communications systems for the purpose of regeneration, multiplexing and switching of the optical signals. As advances in fabrication and packaging techniques are made, the operat­ ing speed will further increase and the cost of production will reach a point where large scale application of GaAs circuits will be economical in these and other systems where speed is paramount. This book is written for students and engineers who wish to enter into this new field of electronics for the first time and who wish to embark on a serious study of the subject of GaAs circuit design. No prior knowledge of GaAs technology is assumed though some previous experience with MOS circuit design will be helpful. A good part of the book is devoted to circuit analysis, to the extent that is possible for non­ linear circuits. The circuit model of the GaAs transistor is derived from first principles and analytic formulas useful in predicting the approxi­ mate circuit performance are also derived. Computer simulation is used throughout the book to show the expected performance and to study the effects of parameter variations.

Contenu

1: Introduction.- 1.1 Gallium Arsenide.- 1.2 Electronic properties of GaAs.- 1.3 Velocity-field relation.- 1.4 GaAs transistor structures, MESFET, HFET, HBT.- 1.5 Scope.- References.- 2: Circuit Models of the MESFET.- 2.1 Introduction.- 2.2 Schottky junction.- Depletion height and capacitance.- Barrier heights.- Current flow across a Schottky junction.- 2.3 Drain current.- Pinch-off voltage.- Threshold voltage.- Velocity-field relation.- Two-region model.- Long-channel, low-field approximation.- Region II.- Saturation drain voltage.- Summary.- 2.4 Gate current.- 2.5 Capacitive currents.- 2.6 Charge-based model for circuit simulation.- 2.7 Capacitance-based model.- 2.8 Parasitic elements.- 2.9 Small signal model.- 2.10 Empirical model.- Current-voltage characteristics.- Charge and capacitance.- 2.11 Summary.- References.- 3: Enhancement-Depletion Logic Circuits.- 3.1 Introduction.- 3.2 Simplified device model for circuit design.- 3.3 E-D logic.- Graphical solution.- Comparison with NMOS inverter.- Noise margins.- Threshold variation.- 3.4 Noise margin analysis.- 3.5 Pull-up delay.- 3.6 Pull-down delay.- 3.7 Fan-out and fan-in.- 3.8 NOR, NAND.- 3.9 Flip flops.- 3.10 Remarks.- References.- 4: Transmission-Gate Logic.- 4.1 Introduction.- 4.2 Analysis.- Turn-on analysis.- Turn-off analysis.- 4.3 Allowable range of VG.- 4.4 Shift register.- 4.5 Cross point switch.- 5: Buffered ED Logic Circuits.- 5.1 Source follower.- DC transfer characteristics.- Pull-up delay.- Pull-down delay.- OR gate.- Simulation results.- 5.2 EDSF logic.- DC transfer characteristics.- Delay.- EDSF NOR.- EDSF buffer.- 5.3 EDSFD logic.- 5.4 EDSB logic.- DC characteristics.- Delay.- NOR gate.- 5.5 SPED logic.- DC characteristics.- Delay.- 5.6 Split-phase super buffer.- 5.7 Ring oscillator.- 5.8 Summary.- References.- 6: Source-Coupled Logic Circuits.- 6.1 Source-coupled differential pair.- 6.2 Observations.- 6.3 Noise margins and delays.- 6.4 Threshold variation.- 6.5 Source-coupled logic.- 6.6 Cascode differential pair.- 6.7 Summary.- Reference.- 7: Subsystems Design.- 7.1 Introduction.- 7.2 Lightwave communications system.- 7.3 Pulse width preservation.- 7.4 Time-multiplexer/demultiplexer.- 7.5 Cross-point switch.- Multiplexer-based design.- Transmission-gate based design.- 7.6 Time- and Time-space-switches.- 7.7 Static random access memory.- Address circuit.- READ circuit.- WRITE circuit.- Improvements.- 7.8 O/E-E/O repeater.- Detector circuit.- Clock extraction circuit.- Decision circuit.- Laser driver.- 7.9 Remarks.- References.