The Designer's Guide to Jitter in Ring Oscillators

The Designer's Guide to Jitter in Ring Oscillators provides information for engineers on designing voltage controlled oscillators (VCOs) and phase-locked loops (PLLs) for low jitter applications such as serial data communication and clock synthesis. The material is presented in a clear, intuitive fashion at both the system level and the circuit level to help designers improve their understanding of fundamental noise sources and design low jitter circuitry within power, area, and process constraints so that ultimate performance meets system level requirements.

At the system level, the authors describe and specify different methods of measuring jitter to characterize time domain uncertainty. Although the emphasis is on time-domain measures of oscillator performance, a simple method of translating performance to frequency domain (phase noise) measures is also included.

At the circuit level, the authors include techniques for design of low jitter delay elements for use in ring oscillators, as well as relating the circuit-level characteristics to system-level performance. The authors discuss a classification scheme for delay stages to help guide the designer's choice with regard to signal type (single-ended vs. differential), output format (single phase vs. multiple phase), and tuning method. Simple mathematical expressions are developed describing the noise-power tradeoffs for each type of stage, so the designer can quickly estimate the power dissipation required to achieve a desired level of jitter.

The Designer's Guide to Jitter in Ring Oscillators is an excellent resource for engineers and researchers interested in jitter and ring oscillators and their application in communication systems.

Résumé
This is a book for engineers concerned with jitter: the e ects of noise visible in the time domain. The material presented will be helpful for work at both the system level and the circuit level: At the system level, the challenge is to describe, specify, and measure time domain uncertainty and when necessary, relate jitter to phase noise speci cations in the frequency domain. At the circuit level, the challenge is to design low noise circuitry within power, area, and process constraints so that ultimate performance meets system level requirements. Throughout the book concepts are presented in the context of an - gineering application requiring low jitter performance: the voltage controlled oscillator (VCO) used in a phase-locked loop (PLL). Techniques are presented for circuit-level design of low jitter delay elements for use in ring oscillators, as well as relating the circuit-level characteristics to system-level performance. Although the emphasis is on time-domain (jitter) measures of oscillator p- formance, a simple method of translating performance to frequency domain (phase noise) measures is presented as well. Structure of this Book This book is divided into nine chapters. The diagram on the following page shows the relationship between material in each chapter as well as placement in the system-level vs. circuit-level design hierarchy. Wherever possible, - perimental veri cation is presented in the same chapter as the corresponding theoretical development, rather than being isolated in a separate chapter.

Contenu
to oscillator jitter.- Classification of ring oscillators.- Phase-Locked Loop System Concepts.- Overview of Noise Analysis Fundamentals.- Measurement Techniques.- Analysis of jitter in ring oscillators.- Sources of jitter in ring oscillators.- Design methodology.- Low jitter VCO design examples.