A Practical Introduction to PSL describes the Property Specification Language PSL, recently standardized as IEEE Std 1850-2005. PSL provides a way to express properties of a design. Both authors, Cindy Eisner (IBM Haifa Research Laboratory, Haifa University Campus, Haifa, Israel) and Dana Fisman (The Weizmann Institute of Science, Rehovot, Israel) were involved with the creation of the standard.

A Practical Introduction to PSL includes extensive examples illustrated with timing diagrams. While mostly oriented to users of PSL for simulation, a section on the use of PSL in formal verification is included. All of the basic language constructs are covered, as well as advanced topics such as the use of PSL in multiply-clocked designs. The chapter on common errors, based on the authors' many years of experience in using and teaching the language, will be helpful to both beginners and more experienced users.

A Practical Introduction to PSL is primarily targeted to hardware designers and verification engineers who plan to use PSL. This book is also of interest to students of temporal logic. The formal semantics of PSL are included as an appendix, and bibliographical notes include pointers to some of the main theoretical works.

From the Foreword:

... "Cindy Eisner and Dana Fisman were the two key people who turned IBM Sugar into PSL. Their deep understanding of PSL's formal semantics was instrumental in both the Accellera and IEEE PSL standardization efforts. Cindy and Dana have now created the most authoritative source for information about PSL, designed to introduce the language incrementally in an easily understood fashion. A Practical Introduction to PSL provides a solid foundation for getting started with PSL today."

Harry Foster - Erich Marschner

Mentor Graphics Corporation Cadence DesignSystems

Résumé
Functional veri?cation is hard. Period. No disagreement here. But why is this so? Consider today's design ?ow: much of it is more or less automated, from RTL to netlist to layout to silicon. But all this automation depends upon having correct RTL input to start with, and there is little or no automation to help with RTL creation. It is hard enough for a designer to decide what RTL model he wants to build, and then to describe that RTL model correctly in a hardware description language. It is even more di?cult for a veri?cation engineer, who can't read the designer's mind, to verify that what the designer created not only represents the RTL model he had conceived, but also that the RTL model is an appropriate one for the problem at hand. What makes RTL modeling and veri?cation di?cult is concurrency. It is easy to teach an engineer how to write procedural code that conforms to the synthesizable subset of a hardware description language. What is hard is understanding how the engineer's procedural code interacts with other c- ponents in the design over time. In fact, until recently we lacked e?ective languages to describe concurrent behaviors. The IEEE 1850 Property Speci?cation Language (PSL) is a language for the formal speci?cation of concurrent systems. The language is particularly applicable for writing assertions about hardware designs. PSL supports m- tiple veri?cation paradigms including formal analysis, simulation, and acc- eration/emulation.

Contenu
Basic Temporal Properties.- Some Philosophy.- Weak vs. Strong Temporal Operators.- SERE Style.- Clocks.- Aborting a Property.- Some Convenient Constructs.- The Simple Subset.- The Boolean, Modeling, and Verification Layers.- Advanced Topics.- More Philosophy High- vs. Low-level Assertions.- Common Errors.- Multiply-clocked Designs.