Low Power Consumption is one of the critical issues in the performance of small battery-powered handheld devices. Mobile terminals feature an ever increasing number of wireless communication alternatives including GPS, Bluetooth, GSM, 3G, WiFi or DVB-H. Considering that the total power available for each terminal is limited by the relatively slow increase in battery performance expected in the near future, the need for efficient circuits is now critical. This book presents the basic techniques available to design low power RF CMOS analogue circuits. It gives circuit designers a complete guide of alternatives to optimize power consumption and explains the application of these rules in the most common RF building blocks: LNA, mixers and PLLs. It is set out using practical examples and offers a unique perspective as it targets designers working within the standard CMOS process and all the limitations inherent in these technologies.
It bridges the lack of specific books for High Frequency design; much of the available literature on low frequency and digital applications do not meet the RF needs
The book takes a practical approach throughout
It gives the reader multiple perspectives covering architecture alternatives, technology features and dedicated schematic circuit techniques
Introduction.- Power Considerations in Analog Rf CMOS Circuits.- Impact of Architecture Selection on RF Front-End Power Consumption.- Technology Structural Alternatives in Standard CMOS Technologies for Low-Power Analog Design.- Schematic Design Techniques for Power Saving in RF.- RF Amplifier Design.- Mixer Design.- Phase Locked Loop (PLL) Design.
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Low Power RF Circuit Design in Standard CMOS Technology