Computer Architecture

Informationen zum Autor ACM named John L. Hennessy a recipient of the 2017 ACM A.M. Turing Award for pioneering a systematic, quantitative approach to the design and evaluation of computer architectures with enduring impact on the microprocessor industry. John L. Hennessy is a Professor of Electrical Engineering and Computer Science at Stanford University, where he has been a member of the faculty since 1977 and was, from 2000 to 2016, its tenth President. Prof. Hennessy is a Fellow of the IEEE and ACM; a member of the National Academy of Engineering, the National Academy of Science, and the American Philosophical Society; and a Fellow of the American Academy of Arts and Sciences. Among his many awards are the 2001 Eckert-Mauchly Award for his contributions to RISC technology, the 2001 Seymour Cray Computer Engineering Award, and the 2000 John von Neumann Award, which he shared with David Patterson. He has also received seven honorary doctorates. Klappentext For over 20 years, Computer Architecture: A Quantitative Approach has beenconsidered essential reading by instructors, students, and practitioners of computer design. The latest edition of this classic textbook is fully revised with the latest developments in processor and system architecture.It nowfeatures examples from the RISC-V ("RISC Five") instruction set architecture, a modern RISC instruction set developedand designedto be afree and openly adoptable standard.It also includesa new chapter on domain-specific architectures and an updated chapter on warehouse-scale computing that features the first public information on Google's newest WSC.True to its originalmission of demystifyingcomputer architecture, the sixth edition of Computer Architecture: A Quantitative Approach continues its longstanding tradition of focusingon the areas where the most exciting computing innovation is happening, while always keeping an emphasis on good engineering design. Inhaltsverzeichnis Printed Text 1. Fundamentals of Quantitative Design and Analysis 2. Memory Hierarchy Design 3. Instruction-Level Parallelism and Its Exploitation 4. Data-Level Parallelism in Vector, SIMD, and GPU Architectures 5. Multiprocessors and Thread-Level Parallelism 6. The Warehouse-Scale Computer 7. Domain Specific Architectures A. Instruction Set Principles B. Review of Memory Hierarchy C. Pipelining: Basic and Intermediate Concepts Online D. Storage Systems E. Embedded Systems F. Interconnection Networks G. Vector Processors H. Hardware and Software for VLIW and EPIC I. Large-Scale Multiprocessors and Scientific Applications J. Computer Arithmetic K. Survey of Instruction Set Architectures L. Advanced Concepts on Address Translation M. Historical Perspectives and References ...

Texte du rabat

For over 20 years, Computer Architecture: A Quantitative Approach has beenconsidered essential reading by instructors, students, and practitioners of computer design. The latest edition of this classic textbook is fully revised with the latest developments in processor and system architecture.It nowfeatures examples from the RISC-V ("RISC Five") instruction set architecture, a modern RISC instruction set developedand designedto be afree and openly adoptable standard.It also includesa new chapter on domain-specific architectures and an updated chapter on warehouse-scale computing that features the first public information on Google's newest WSC.True to its originalmission of demystifyingcomputer architecture, the sixth edition of Computer Architecture: A Quantitative Approach continues its longstanding tradition of focusingon the areas where the most exciting computing innovation is happening, while always keeping an emphasis on good engineering design.

Résumé

"What has made this book an enduring classic is that each edition is not an update, but an extensive revision that presents the most current information and unparalleled insight into this fascinating and fast changing field. For me, after over twenty years in this profession, it is also another opportunity to experience that student-grade admiration for two remarkable teachers." --From the Foreword by Luiz Andre Barroso, Google, Inc.

Contenu

Printed Text 1. Fundamentals of Quantitative Design and Analysis 2. Memory Hierarchy Design 3. Instruction-Level Parallelism and Its Exploitation 4. Data-Level Parallelism in Vector, SIMD, and GPU Architectures 5. Multiprocessors and Thread-Level Parallelism 6. The Warehouse-Scale Computer 7. Domain Specific Architectures A. Instruction Set Principles B. Review of Memory Hierarchy C. Pipelining: Basic and Intermediate Concepts

Online D. Storage Systems E. Embedded Systems F. Interconnection Networks G. Vector Processors H. Hardware and Software for VLIW and EPIC I. Large-Scale Multiprocessors and Scientific Applications J. Computer Arithmetic K. Survey of Instruction Set Architectures L. Advanced Concepts on Address Translation M. Historical Perspectives and References