This book presents a rigorous and practically grounded treatment of jitter and spur minimization in fractional-N digital phase locked loops (DPLLs), addressing one of the most critical challenges in modern frequency synthesis. Bridging the gap between theoretical analysis and design practice, it introduces a unified framework for modeling quantization and nonlinear effects in time-to-digital converters and digital-to-time converters, enabling accurate prediction of phase noise, jitter, and spurious tones across integer-N and fractional-N operation. Unlike conventional approaches, the methods developed in this work explicitly account for the interaction between systematic nonlinearities and the statistical properties of steady-state quantization error signals, establishing clear validity limits for widely used linearized models. The book further provides comprehensive system-level design methodologies that achieve minimum jitter with minimal hardware overhead. Supported by companion MATLAB source codes for behavioral modeling and analysis, it offers readers a reproducible and extensible toolkit for exploring and optimizing advanced fractional-N DPLLs. Combining analytical rigor, practical relevance, and broad applicability, this book serves as both a reference and a hands-on guide for researchers and engineers in frequency synthesis and mixed-signal integrated circuit design.

Describes A Matlab-based modelling framework for all-digital phase-locked loops (ADPLLs) Uses theoretical and intuitive explanations of spur production mechanisms Includes methods for identifying spurs resulting from soft and hard nonlinearities

Autorentext

Xu Wang was born in Qingdao, China. He received the M.Eng. degree (incorporating Bachelor's level study) in Electrical and Electronic Engineering from Imperial College London, UK, in 2019, and the Ph.D. degree from University College Dublin (UCD), Ireland, in 2024. Dr. Wang is currently an Assistant Professor with UCD. In 2018, he was with MediaTek Inc., Kent, UK, for design modeling and verification of a flagship 5G multi-mode SoC RFIC. At UCD, he has been a Research Assistant Pending Viva (2024), Postdoctoral Research Fellow (2024), and Assistant Professor Above the Bar (2025). His research interests include high-performance frequency synthesizers, analog and digital phase locked loops, digital Delta-Sigma modulators, and design and modeling of analog/RF/mixed-signal circuits and systems. Dr. Wang was a recipient of the IEEE CASS Student Travel Grants in 2023 and 2024 and the IEEE ISCAS Predoctoral Travel Grant in 2024. He received the 2023 China National Award for Outstanding Self-financed Students Abroad for his Ph.D. research achievement. He has authored two papers selected as Highlights of IEEE Transactions on Circuits and Systems—I: Regular Papers (TCAS-I) in 2023 Dec. and 2025 Mar. issues. He serves as an invited reviewer for various journals and conferences in the field. Michael Peter Kennedy received the B.E. degree in electronics from the National University of Ireland, Dublin, in 1984, and the M.S. and Ph.D. degrees from the University of California (UC Berkeley), Berkeley, in 1987 and 1991, and the DEng degree from the National University of Ireland in 2010. He was made an IEEE Fellow in 1998 for his contributions to the study of Neural Networks and Nonlinear Dynamics. He received an honorary DSc degree in Engineering from the Queen's University of Belfast in 2020. He worked as a Design Engineer with Philips Electronics, a Postdoctoral Research Engineer at the Electronics Research Laboratory, UC Berkeley, and as a Professeur Invité at the Federal Institute of Technology Lausanne (EPFL), Switzerland. From 1992 to 2000, he was on the faculty of the Department of Electronic and Electrical Engineering at University College Dublin (UCD), Dublin, Ireland, where he taught electronic circuits and computer-aided circuit analysis and directed the undergraduate Electronics Laboratory. In 2000, he joined University College Cork (UCC), Cork, Ireland, as Professor and Head of the Department of Microelectronic Engineering. He was Dean of the Faculty of Engineering at UCC from 2003 to 2005 and Vice-President for Research from 2005 through 2010. He returned to UCD as Professor of Microelectronic Engineering in 2017. He was a founding Director of Ireland's Microelectronics Industry Design Association in 2001 and was Scientific Director of the Microelectronic Circuits Centre Ireland from 2010 through 2024. He has over 400 publications in the area of nonlinear circuits and has taught courses on nonlinear dynamics and delta-sigma modulation in China, England, Greece, Hungary, Italy, Korea, Spain, Switzerland, and the USA. His research interests are in the simulation, analysis and design of nonlinear dynamical systems for applications in communications and signal processing. Dr. Kennedy was the recipient of the 1991 Best Paper Award from the International Journal of Circuit Theory and Applications and the Best Paper Award at the European Conference on Circuit Theory and Design 1999. He served as Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS from 1993 to 1995 and from 1999 to 2004. He was awarded the IEEE Third Millennium Medal, the IEEE Circuits and Systems Society Golden Jubilee Medal in 2000, the inaugural Parson's Medal for Engineering Sciences by the Royal Irish Academy (RIA) in 2001, UCC Invention of the Year 2011 and UCD Licence of the Year 2025. He was elected to membership of the RIA in 2004, served as RIA Policy and International Relations Secretary from 2012 through 2016, and as Pre

Inhalt

Introduction.- Simulation Methodology for Digital Phase-Locked Loops.- Linearized Analysis of TDCs.- Prediction of System Jitter and Output PN.- Jitter Minimization for Integer-N PLLs and Its Impact on Output PN.- Introduction and Analysis of DTC.- Strategies to Minimize DTC-Related Spurs.- Conclusions.