Presenting a mathematical model for on-chip routers which can be used for NoC performance analysis, this book reflects the shift from computation- to communication-based design that has resulted from the increasing complexity of so-called 'systems-on-chip'.

Traditionally, design space exploration for Systems-on-Chip (SoCs) has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip and their performance continue to increase, the communication architecture plays a major role in the area, performance and energy consumption of the overall system. As a result, a shift from computation-based to communication-based design becomes mandatory. Towards this end, network-on-chip (NoC) communication architectures have emerged recently as a promising alternative to classical bus and point-to-point communication architectures.

In this dissertation, we study outstanding research problems related to modeling, analysis and optimization of NoC communication architectures. More precisely, we present novel design methodologies, software tools and FPGA prototypes to aid the design of application-specific NoCs.

Presented is a mathematical model for on-chip routers and use this model for NoC performance analysis Our performance analysis approach can be used not only to obtain fast and accurate performance estimates, but also to guide the NoC design process within an optimization loop, since it can be performed much faster than simulation Presented is a methodology to automatically synthesize an NoC architecture which is a superposition of a few long-range links and a standard mesh network The few application-specific longrange links we insert significantly increase the critical traffic workload at which the network transitions from a free to a congested state This way, we can exploit the benefits offered by both complete regularity and partial topology customization Considered is a flow control algorithms specifically developed for NoCs and propose a predictive closed-loop flow control mechanism Our technique controls the packet injection rate at traffic sources in order to regulate the total number of packets in the network Experiments on an FPGA prototype and simulation results demonstrate that significant reduction in the average and maximum packet latency is achieved due to the proposed controller Increasing energy consumption and synchronization are major problems in the design of NoCs To this end, we present a design methodology for partitioning an NoC architecture into multiple voltage-frequency islands (VFIs) and assigning supply and threshold voltage levels to each VFI Simulation results show about 40% savings for a real video application.VFIs Finally, we support our theoretical findings by actual FPGA-based implementations Includes supplementary material: sn.pub/extras

Inhalt
Introduction.- Literature Survey.- Motivational Example: MPEG-2 Encoder Design.- Target NoC Platform.- NoCPerformance Analysis.- Application-specific NoC Architecture Custimization using Long-range Links.- Analysis and Optimization of Prediction-based Flow Control in Networks-on-Chip.- Design and Management of VFI Partition Networks-on-Chip.- Conclusion.- Bibliography.- Appendix A. Tools and FPGA prototype.- Appendix B. Experiments using the Single-chip Cloud Computer (SCC) Platform.