This book brings together a selection of the best papers from the thirteenth edition of the Forum on specification and Design Languages Conference (FDL), which was held in Southampton, UK in September 2010. FDL is a well established international forum devoted to dissemination of research results, practical experiences and new ideas in the application of specification, design and verification languages to the design, modelling and verification of integrated circuits, complex hardware/software embedded systems, and mixed-technology systems.

Covers design verification, automatic synthesis and mechanized debug aids Includes language-based modeling and design techniques for embedded systems Covers design, modeling and verification of mixed physical domain and mixed signal systems that include significant analog parts in electrical and non-electrical domains Includes formal and semi-formal system level design methods for complex embedded systems based on the Unified Modelling Language (UML) and Model Driven Engineering (MDE) Includes supplementary material: sn.pub/extras

Inhalt
Formal Hardware/Software Co-verification of Application Specific Instruction Set Processors.- Evaluating Debugging Algorithms from a Qualitative Perspective.- Mapping of Concurrent Object-oriented Models to Extend Real-time Task Networks.- SystemC-A Modelling of Mixed-technology Systems with Distributed Behaviour.- A Framework for Interactive Refinement of Mixed HW/SW/Analog Systems.- Bottom-up Verification for CMOS Photonic Linear Heterogeneous System.- Towards Abstract Analysis Techniques for Range Based System Simulations.- Modeling Time-triggered Architecture Based Real-time Systems Using SystemC.- Towards the Development of a Set of Transaction Level Models - A Feature-oriented Approach.- Rapid Prototyping of Complex HW/SW Systems Using a Timing and Power Aware ESL Framework.- Towards Accurate Source-level Annotation of Low-level Properties Obtained from Optimized Binary Code.- Architecture Specifications in CaSH.- SyReC: A Programming Language for Synthesis of Reversible Circuits.- Logical Time @ Work: Capturing Data Dependencies and Platform Constraints.- Formal Support for Untimed MARTE-SystemC Interoperability.