This book provides a structured and comprehensive pathway through the complexities of Electronic Design Automation (EDA) tools and processes. It focuses on OpenLane and Caravel EDA tools, due to their current major role in the open-source IC design ecosystem. OpenLane provides a robust and flexible platform that automates the entire digital design flow from Register Transfer Level (RTL) to Graphic Data System II (GDSII), making it an ideal tool for teaching and learning the physical design process. Caravel, on the other hand, serves as an open-source System on a Chip (SoC) platform, allowing designers to integrate and test their designs in a versatile, real-world environment. It complements OpenLane by enabling users to package and validate their designs, bridging the gap between theoretical knowledge and practical implementation. Together, these tools provide a way to understand the full tape-out process in a way that is accessible to students, researchers, and professionals alike.

Provides a structured and comprehensive pathway through the complexities of EDA tools and processes Focuses on OpenLane and Caravel EDA tools, due to their current major role in the open-source IC design ecosystem Written for students, researchers, and professionals aiming to deepen their understanding of advanced IC design concepts

Autorentext

Pedro Mejia-Alvarez received his BSc degree in computer systems from ITESM, Querétaro, Mexico, in 1985, his PhD degree in Informatics from the Polytechnic University of Madrid, Spain, in 1995. He pursued his PostDoc Research at the Computer Science Department of the University of Pittsburgh in 1999-2000. He has been a Professor with the CINVESTAV-Guadalajara since 1997. His research interests include Real-Time Systems, Software Testing and Software Engineering. Raul E. Gonzalez Torres received his PhD in Mathematics from the University of Houston in 1987. His research interests are Formal Software Verification, Automatic Theorem Proof, Demonstration Theory for non-classical Logics and Applications of Logic in Engineering and Computing. Susana Ortega-Cisneros received her BSc degree in communications and electronics from the Universidad de Guadalajara, México, in 1990, the MSc degree from the Center for Research and Advanced Studies (CINVESTAV), México City, México, and the PhD degree in computer science and telecommunications from the Autonomous University of Madrid, Spain. She is currently with CINVESTAV and specializes in the design of digital architectures based on field-programmable gate arrays (FPGAs), DSPs, and microprocessors.

Inhalt

1: Introduction.- 2: Physical Design Flow.- 3: Process Design Kit.- 4: Introduction to OpenLane.- 5: Macro-Cells and RAM-Cells with OpenLane.- 6: Exploring OpenLane through Case Studies and Exercises.- 7: Caravel.