This book covers analysis and design of PLL-based frequency modulators, used in the hearth of modern FMCW radars. The desired radar performance targets are translated into the modulator specifications first. The authors then focus on describing the optimal modulator architecture, with special care given to core building blocks of the system. The central analog building block described is a novel charge integrating-based chirp generator, which breaks limits of similar art in the field where performance (noise, area) is typically traded for power. The book then continues to describe power-efficient, mixed-signal background calibration engine implementation, which when applied in context of the presented system, ensures pristine linearity of the generated chirps. The detailed design guide shows how robust duty-cycling can be enabled, to ensure low-power consumption of the system, without compromise in radar performance. A complete overview of all circuit-level building blocks is provided, to ensure that readers can tackle every aspect of the system. Finally, the book covers description of a rigorous chirp-linearity and phase-noise performance characterization methodology, critical for evaluation of radar system performance metrics.

This book provides insightful design guidelines for DTC-based fractional-N PLL synthesizers and QDAC-based FMCW frequency modulators for both academic researchers and industry IC design engineers.

Autorentext

Pratap Tumkur Renukaswamy received the M.Sc. degree in integrated systems and circuits design from the Carinthia University of Applied Sciences, Villach, Austria, in 2016, and the Ph.D. degree from Vrije Universiteit Brussel, Brussels, Belgium, in 2023. His PhD research was focused on frequency synthesis for FMCW radar application. He is currently a researcher at imec, Leuven, Belgium, working on mixed-signal circuits for frequency synthesis and analog-to-digital converters. Nereo Markulic received the M.Sc. degree in electrical engineering from the University of Zagreb, Zagreb, Croatia, in 2012, and the Ph.D. degree summa cum laude from Vrije Universiteit Brussel, Brussels, Belgium, in 2018. His Ph.D. work was in collaboration with the Interuniversity Microelectronics Center (imec), Leuven, Belgium, on digital subsampling phase-locked loops (PLLs) and polar transmitters. He is currently a Research Scientist with imec, working on RF and mixed-signal circuits for radar applications and next generation connectivity. He has authored and coauthored publications and patents on PLLs and analog-to-digital converters and a book on frequency synthesis. Dr. Markulic currently serves on the Technical Program Committee for the Symposia on VLSI Technology and Circuits. He is a co-recipient of the ISSCC 2019 Lewis Winner Award for Outstanding Paper. Jan Craninckx obtained his Ms. and Ph.D. degree in microelectronics summa cum laude from the ESAT-MICAS laboratories of the KULeuven in 1992 and 1997, respectively. His Ph.D. work was on the design of low-phase noise CMOS integrated VCOs and PLLs for frequency synthesis. From 1997 till 2002 he worked with Alcatel Microelectronics (later part of STMicroelectronics) as a senior RF engineer on the integration of RF transceivers for GSM, DECT, Bluetooth and WLAN. In 2002 he joined IMEC (Leuven, Belgium) as principal scientist working on RF, analog and mixed signal circuit design. He is currently IMECfellow. His research focuses on the design of RF transceiver front-ends in nanoscale CMOS, covering all aspects of RF, mmwave, analog and data converter design. Dr. Craninckx is an IEEE Fellow and has authored and co-authored more than 200 papers, book chapters, and patents. He is/was a regular member of the Technical Program Committee for several IEEE SSCS conferences, was the chair of the SSCS Benelux chapter (2006-2011), SSCS Distinguished Lecturer (2012-2013), and elected SSCS AdCom member (2017-2019). He received the received the ISSCC 2015 Jan Van Vessem Award and the ISSCC 2019 Lewis Winner Award. He was Associate Editor (2009-2016) and Editor-in-Chief (2016-2019) of the IEEE Journal of Solid-State Circuits.

Inhalt

Introduction.- A 10GHz Sub Sampling PLL Chirp Synthesizer using a Charge.- Integrating Digital-to-Analog Converter (DAC).- A 16 GHz Duty-Cycled Charge Pump PLL-based Chirp Synthesizer.- Conclusion.