This book explains concepts behind fractional subsampling-based frequency synthesis that is re-shaping today's art in the field of low-noise LO generation. It covers advanced material, giving clear guidance for development of background-calibrated environments capable of spur-free synthesis and wideband phase modulation. It further expands the concepts into the field of subsampling polar transmission, where the newly developed architecture enables unprecedented spectral efficiency levels, unquestionably required by the upcoming generation of wireless standards.

Guides development of DTC-based Fractional-N Subsampling PLL and Subsampling Polar Transmitters, covering material from fundamental theory, over system level considerations to building block IC implementation Describes a fully background-calibrated environment that can used in general context of fractional frequency synthesis and/or phase/frequency modulation Presents three IC implementations, showing system level analysis, design methodology, circuit details and measurement results

Autorentext
Nereo Markulic was born in 1988 in Rijeka, Croatia. He received M.Sc. degree (2012) in electrical engineering from University of Zagreb, Croatia and a Ph.D. degree (2018) summa cum laude from Vrije Universiteit Brussel, Belgium. His Ph.D. work was in collaboration with imec, Belgium on digital subsampling PLLs and Polar Transmitters. He is currently a researcher in imec, Belgium. His research interest includes data converters, frequency synthesis and transceivers for next generation wireless communication. Kuba Raczkowski received the M.Sc. degree in electrical engineering from Warsaw University of Technology, Warsaw, Poland, in 2006, and the Ph.D. degree from K.U.Leuven, Belgium, in 2011 for his work on 60 GHz phased-array circuits and systems. Since then he has been with imec, Leuven, Belgium, working on high-performance RF synthesizers. Currently, he is part of the team developing custom,specialty imagers. Jan Craninckx obtained his Ms. and Ph.D. degree in microelectronics summa cum laude from the ESAT-MICAS laboratories of the Katholieke Universiteit Leuven in 1992 and 1997, respectively. His Ph.D. work was on the design of low-phase noise CMOS integrated VCOs and PLLs for frequency synthesis. From 1997 till 2002 he worked with Alcatel Microelectronics (later part of STMicroelectronics) as a senior RF engineer on the integration of RF transceivers for GSM, DECT, Bluetooth and WLAN. In 2002 he joined IMEC (Leuven, Belgium) as principal scientist responsible for RF, analog and mixed signal circuit design, where he is currently Distinguished Member of Technical Staff. His research focuses on the design of RF transceiver front-ends in nanoscale CMOS, covering all aspects of RF, analog and data converter design. Dr. Craninckx is an IEEE Fellow and has authored and co-authored more than 200 papers, book chapters, and patents. He is/was a regular member of the Technical Program Committee for several SSCS conferences, was the chair of the SSCS Benelux chapter (2006-2011), SSCS Distinguished Lecturer (2012-2013), and elected SSCS AdCom member (2017-2019). He was Associate Editor (2009-2016) and currently serves as Editor-in-Chief of the IEEE Journal of Solid-State Circuits. Piet Wambacq received the M.Sc. degree in electrical engineering and Ph.D. degree from the Katholieke Universiteit Leuven, Leuven, Belgium, in 1986 and 1996, respectively. He joined imec, Leuven, Belgium in 1996 as a Principal Scientist and he is now a Distinguished Member of Technical Staff, working on IC design in various technologies for wireless applications. Since 2000 he is a Professor with the Vrije Universiteit Brussel (VUB), Brussels, Belgium. He has authored or co-authored three books and more than 250 papers in edited books, international journals and conferences. He has been an associate editor of the IEEE Transactions on Circuits and Systems - Part 1 from 2002to 2004. He was the co-recipient of the Best Paper Award at the Design, Automation and Test Conference (DATE) in 2002 and 2005, the EOS/ESD Symposium in 2004 and the Jan Van Vessem Award" for "Outstanding European Paper" at ISSCC 2015. He was a member of the program committee of the DATE conference from 2000 to 2007. He is currently a member of the program committee of ESSCIRC and he chairs the RF subcommittee of ISSCC. He is a senior member of IEEE and Distinguished Lecturer of The Solid-State Circuits Society of IEEE.

Inhalt

Chapter 1. Introduction.- Chapter 2. A Digital-to-Time Converter based Subsampling PLL for Fractional Synthesis.- Chapter 3. A Background-Calibrated Subsampling PLL for Phase/Frequency Modulation.- Chapter 4. A Background-Calibrated Digital Subsampling Polar Transmitter.- Chapter 5. Conclusion and Future Outlook.