This book describes techniques for time-interleaving a number of analog-to-digital data converters to achieve demanding bandwidth requirements. Readers will benefit from the presentation of a low-power solution that can be used in actual products, while alleviating the time-varying signal artifacts that typically arise when implementing such a system architecture.

Discusses time-interleaved ADC theory in detail Presents and analyzes a full solution for timing-skew in time-interleaved ADCs Demonstrates how to optimize the design of a time-interleaved ADC for extremely low-power and very high sample rate Includes supplementary material: sn.pub/extras

Autorentext

Manar El-Chammas received his Ph.D. from Stanford University in 2010, where his research focused on multi-GS/s time-interleaved ADCs. He joined Texas Instruments in 2010, where he worked on high-speed and high-performance ADCs for wireless infrastructure, and was the design manager of the High Speed Data Converter group. He later joined Mythic as the Director of Analog Design, where he led the development of the core analog computation engine for neural networks. Afterwards, he worked at an early stage startup architecting novel artificial intelligence inference systems. He then joined Omni Design Technologies, and is currently SVP of Engineering focused on ultra-high speed data converter architectures. He has been granted multiple patents in high-speed ADC design and mixed-signal computation, has published and presented a variety of journal and conference articles (and was the recipient of the best paper award at IEEE BCTM), and has written a book on time-interleaved ADCs.. His research interests include highly linear sampling systems, ultra-low power data converter design, and efficient computation systems for machine learning.

Inhalt
Introduction.- Time-Interleaved ADCs.- Mitigation of Timing Skew.- Architecture Optimization.- Circuit Design.- Measurement Results.- Conclusion.