This book proposes probabilistic machine learning models that represent the hardware properties of the device hosting them. These models can be used to evaluate the impact that a specific device configuration may have on resource consumption and performance of the machine learning task, with the overarching goal of balancing the two optimally.

The book first motivates extreme-edge computing in the context of the Internet of Things (IoT) paradigm. Then, it briefly reviews the steps involved in the execution of a machine learning task and identifies the implications associated with implementing this type of workload in resource-constrained devices. The core of this book focuses on augmenting and exploiting the properties of Bayesian Networks and Probabilistic Circuits in order to endow them with hardware-awareness. The proposed models can encode the properties of various device sub-systems that are typically not considered by other resource-aware strategies, bringing about resource-saving opportunities that traditional approaches fail to uncover.

The performance of the proposed models and strategies is empirically evaluated for several use cases. All of the considered examples show the potential of attaining significant resource-saving opportunities with minimal accuracy losses at application time. Overall, this book constitutes a novel approach to hardware-algorithm co-optimization that further bridges the fields of Machine Learning and Electrical Engineering. ** ****

Introduces a new, systematic approach for the realization of hardware-awareness with probabilistic models Enables readers to accommodate various systems and applications, as demonstrated with multiple use cases targeting distinct types of devices Describes novel methods to deal with some of the challenges of extreme-edge computing, a paradigm that has recently garnered attention as a complementary approach to cloud computing Represents one of the first efforts systematically to bring probabilistic inference to the world of edge computing, by means of novel algorithmic insights and strategies

Autorentext
Laura Isabel Galindez Olascoaga obtained her M.Sc. degree in Systems and Control from the Technical University of Eindhoven, The Netherlands, in 2015 and her Ph.D. degree in Electrical Engineering from KU Leuven, Belgium, in 2020. During the winter of 2018, she was a visiting scholar at the Statistical and Relational Artificial Intelligence (StarAI) lab of UCLA. She is currently a postdoctoral researcher at the Berkeley Wireless Research Center (BWRC) in UC Berkeley, where she investigates how to exploit the paradigm of Hyperdimensional Computing in applications that require intelligent feedback loops. Wannes Meert received his degrees of Master of Electrotechnical Engineering, Micro-electronics (2005), Master of Artificial Intelligence (2006) and Ph.D. in Computer Science (2011) from KU Leuven. He is a research manager in the DTAI section at KU Leuven. His work is focused on applying machine learning, artificial intelligence and anomaly detection technology to industrial application domains. Marian Verhelst is an associate professor at the MICAS laboratories of the EE Department of KU Leuven. Her research focuses on embedded machine learning, hardware accelerators, HW-algorithm co-design and low-power edge processing. Before that, she received a PhD from KU Leuven in 2008, was a visiting scholar at the BWRC of UC Berkeley in the summer of 2005, and worked as a research scientist at Intel Labs, Hillsboro OR from 2008 till 2011. Marian is a member of the DATE and ISSCC executive committees, is TPC co-chair of AICAS2020 and tinyML2020, and TPC member DATE and ESSCIRC. Marian is an SSCS Distinguished Lecturer, was a member of the Young Academy of Belgium, an associate editor for TVLSI, TCAS-II and JSSC and a member of the STEM advisory committee to the Flemish Government. Marian currently holds a prestigious ERC Starting Grant from the European Union and was the laureate of the Royal Academy of Belgium in 2016.

Inhalt

Introduction.- Background.- Hardware-Aware Cost Models.- Hardware-Aware Bayesian Networks for Sensor Front-End Quality Scaling.- Hardware-Aware Probabilistic Circuits.- Run-Time Strategies.- Conclusions.