The need of video compression in the modern age of visual communication cannot be over-emphasized. This monograph will provide useful information to the postgraduate students and researchers who wish to work in the domain of VLSI design for video processing applications. In this book, one can find an in-depth discussion of several motion estimation algorithms and their VLSI implementation as conceived and developed by the authors. It records an account of research done involving fast three step search, successive elimination, one-bit transformation and its effective combination with diamond search and dynamic pixel truncation techniques. Two appendices provide a number of instances of proof of concept through Matlab and Verilog program segments. In this aspect, the book can be considered as first of its kind. The architectures have been developed with an eye to their applicability in everyday low-power handheld appliances including video camcorders and smartphones.

Provides recent research and useful information for researchers and students working in the field of VLSI design for video processing applications Presents recent research in fast three step search, successive elimination, one-bit transformation and its effective combination with diamond search and dynamic pixel truncation techniques Explains applications in everyday low-power handheld appliances including video camcorders and smartphones Includes two appendices providing a number of instances of proof of concept through Matlab and Verilog program segments Includes supplementary material: sn.pub/extras

Inhalt

Introduction.- Background and Literature Survey.- VLSI Architecture for Fast Three Step Search Algorithm.- Parallel Architecture for Successive Elimination Block Matching Algorithm.- Fast One-Bit Transformation Architectures.- Efficient Pixel Truncation Algorithm and Architecture.- Introduction to Scalable Image and Video Coding.- Forward Plans.- 8 Forward Plans.- A Matlab Programs.- B Verilog Modules.