Formal Methods for Hardware Verification

Klappentext

This book presents 8 papers accompanying the lectures of leading researchers given at the 6th edition of the International School on Formal Methods for the Design of Computer, Communication and Software Systems (SFM 2006). SFM 2006 was devoted to formal techniques for hardware verification and covers several aspects of the hardware design process, including hardware design languages and simulation, property specification formalisms, automatic test pattern generation, symbolic trajectory evaluation, and more.

Inhalt
Hardware Design and Simulation for Verification.- Automatic Test Pattern Generation.- An Introduction to Symbolic Trajectory Evaluation.- BDD-Based Hardware Verification.- SAT-Based Verification Methods and Applications in Hardware Verification.- Building Efficient Decision Procedures on Top of SAT Solvers.- Refinement and Theorem Proving.- Floating-Point Verification Using Theorem Proving.