SOC test design and its optimization is the topic of this book, and the aim is to give an introduction to testing, describe the problems related to SOC testing, discuses the modeling granularity and the implementation into EDA (electronic design automation) tools. It first introduces readers to test problems including faults, fault types, design-flow, design-for-test techniques such as scan-testing and Boundary Scan. Then it discusses SOC related problems such as system modeling, test conflicts, power consumption, test access mechanism design, test scheduling and defect-oriented scheduling. The final part focuses on SOC applications, such as integrated test scheduling and TAM design, defect-oriented scheduling, and integrating test design with core selection process. Intended for graduate students and PhD-students working in the test field, the manual also aids researchers and professors who would like to get into the area of SOC testing.

System perspective to SOC test design. Overview of test problems and their modeling Test scheduling overview, extensive reference list Applicable for Master students and PhD-students working in the test field. Could also be good for researchers and professors who would like to get into the area of SOC testing, also for persons in the field who want some references Includes supplementary material: sn.pub/extras

Autorentext

Dr. Erik Larsson is an assistant professor at Linköpings University in Sweden, and he is an active member of the IEEE Testing and Circuits & Systems societies

Inhalt
Testing Concepts.- Design Flow.- Design for Test.- Boundary Scan.- SOC Design for Testability.- System Modeling.- Test Conflicts.- Test Power Dissipation.- Test Access Mechanism.- Test Scheduling.- SOC Test Applications.- A Reconfigurable Power-Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling.- An Integrated Framework for the Design and Optimization of SOC Test Solutions.- Efficient Test Solutions for Core-Based Designs.- Core Selection in the SOC Test Design-Flow.- Defect-Aware Test Scheduling.- An Integrated Technique for Test Vector Selection and Test Scheduling under ATE Memory Depth Constraint.