Dynamic System Reconfiguration in Heterogeneous Platforms defines the MORPHEUS platform that can join the performance density advantage of reconfigurable technologies and the easy control capabilities of general purpose processors. It consists of a System-on-Chip made of a scalable system infrastructure hosting heterogeneous reconfigurable accelerators, providing dynamic reconfiguration capabilities and data-stream management capabilities.

Fine/coarse-grain architectural elements connected by a network on chip Software-like design tool flow for dynamically reconfigurable platform Full set of industrial applications Unique development to true silicon

Klappentext

Dynamic System Reconfiguration in Heterogeneous Platforms defines the MORPHEUS platform that can join the performance density advantage of reconfigurable technologies and the easy control capabilities of general purpose processors. It consists of a System-on-Chip made of a scalable system infrastructure hosting heterogeneous reconfigurable accelerators, providing dynamic reconfiguration capabilities and data-stream management capabilities.

Moreover a toolset which offers a software-oriented approach for implementing data intensive applications on the chip is presented. The toolset provides application design process based on high level programming languages as much as possible.

Various applications from differnt domains have been selected to drive the development of the project in assessing the MORPHEUS concept about its computing performance, utilization flexibility and productivity.

The emerging IEEE 802.16j standard for Mobile Broadband Wireless Access systems is the base for a first type of applications. The second application is in the area of telecommunication networks which requires data rates up to 40 Gbit/s per single line. A third application is about huge digital postprocessing of the films captured by digital camera or film scanners in resolutions up to 4K. The fourth application is about image processing for intelligent cameras.

Inhalt
to MORPHEUS.- State of the Art.- The MORPHEUS Architecture.- MORPHEUS Architecture Overview.- Flexeos Embedded FPGA Solution.- The Dream Digital Signal Processor.- XPP-III.- The Hardware Services.- The MORPHEUS Data Communication and Storage Infrastructure.- The Integrated Tool Chain.- Overall MORPHEUS Toolset Flow.- The Molen Organisation and Programming Paradigm.- Control of Dynamic Reconfiguration.- Specification Tools for Spatial Design.- Spatial Design.- The Applications.- Real-Time Digital Film Processing.- Ethernet Based In-Service Reconfiguration of SoCs in Telecommunication Networks.- Homeland Security Image Processing for Intelligent Cameras.- PHY-Layer of 802.16 Mobile Wireless on a Hardware Accelerated SoC.- Concluding Section.- Conclusions.- Training.- Dissemination of MORPHEUS Results.- Exploitation from the MORPHEUS Project.- Project Management.