Partial Reconfiguration on FPGAs

This book focuses on design of run-time reconfigurable systems on Field-Programmable Gate Arrays (FPGAs), showing how to gain resource and power efficiency, as well as to improve speed. Case studies guide readers through the FPGA jungle toward a working system.

This is the first book to focus on designing run-time reconfigurable systems on FPGAs, in order to gain resource and power efficiency, as well as to improve speed. Case studies in partial reconfiguration guide readers through the FPGA jungle, straight toward a working system. The discussion of partial reconfiguration is comprehensive and practical, with models introduced together with methods to implement efficiently the corresponding systems. Coverage includes concepts for partial module integration and corresponding communication architectures, floorplanning of the on-FPGA resources, physical implementation aspects starting from constraining primitive placement and routing all the way down to the bitstream required to configure the FPGA, and verification of reconfigurable systems.

Provides comprehensive overview of state-of-the-art partial run-time reconfiguration techniques, including architectures, methods, and tools Focuses on real applications that will benefit from partial reconfiguration Describes methods and tools to implement efficient, reconfigurable systems that can substantially improve cost, power consumption, or speed (throughput/latency) Includes practical use-cases that act as design patterns for a wide range of applications

Autorentext
Introduction.- Intra-FPGA Communication Architectures for Reconfigurable Systems.- Building Partially Reconfigurable Systems: Methods and Tools.- Self-adaptive Reconfigurable Networks.- Reconfigurable CPU Instruction Set Extensions.- Concluding Remarks.

Inhalt
Preemptive Hardware Task execution.- Intra-FPGA Communication Architectures for Reconfigurable Systems.- Building Partially Reconfigurable Systems Methods and Tools.- Applications and Use Cases.