Closing the Power Gap between ASIC & Custom

Until recently, ASIC designers have mostly focused on how to achieve the desired performance requirements, and the typical ASIC design flow pays limited attention to power. In comparison, some custom designs have significantly advanced techniques for low power, such as voltage islands, substrate biasing, and sleep mode power gating. Butt custom designed chips can achieve low power at the same performance compared to ASIC chips designed in an EDA flow. In Closing the POWER Gap between ASIC & Custom, the significance of different low power design approaches is explored in detail. This book covers how to use low power design approaches in an automated design flow, and examine the design time and performance trade-offs of low power design. After chapter which outline factors affecting the power consumption of ASIC and custom designs and explore how each factor can contribute to custom designs being lower power than ASICs, the book focuses on the latest tools and techniques for low power design that may be applied in an ASIC design flow.

Will cover how to use low power design in an automated design flow, and examine the design time and performance trade-offs Includes the latest tools and techniques for low power design applied in an ASIC design flow Focuses on low power in an automated design methodology; a much neglected area Includes supplementary material: sn.pub/extras

Zusammenfassung
This book carefully details design tools and techniques for realizing low power and energy efficiency in a highly productive design methodology.

Important topics include:

• Microarchitectural techniques to reduce energy per operation
• Power reduction with timing slack from pipelining
• Analysis of the benefits of using multiple supply and threshold voltages
• Placement techniques for multiple supply voltages
• Verification for multiple voltage domains
• Improved algorithms for gate sizing, and assignment of supply and threshold voltages
• Power gating design automation to reduce leakage
• Relationships among tatistical timing, power analysis, and parametric yield optimization

Design examples illustrate that these techniques can improve energy efficiency by two to three times.

Inhalt
Overview of the Factors Affecting the Power Consumption.- Pipelining to Reduce the Power.- Voltage Scaling.- Methodology to Optimize Energy of Computation for SOCs.- Linear Programming for Gate Sizing.- Linear Programming for Multi-Vth and Multi-Vdd Assignment.- Power Optimization using Multiple Supply Voltages.- Placement for Power Optimization.- Power Gating Design Automation.- Verification For Multiple Supply Voltage Designs.- Winning the Power Struggle in an Uncertain Era.- Pushing ASIC Performance in a Power Envelope.- Low Power ARM 1136JF-S Design.