Clock-skew errors in time-interleaved ADCs importantly degrade the linearity of such converters. These nearly constant but unknown errors lead time-interleaved ADCs into periodical non-uniform sampling. There are some techniques of facing clock-skew errors: two-ranks sample-and-hold, channel randomization, global passive sampling, clock-edge reassignment, all-digital and all-analog calibration techniques. We propose a new kind of mixed-signal clock-skew calibration technique that distinguishes itself by the simplicity of its analog components while keeping the inherent robustness of digital clock-skew detections. A demonstrator shows the feasibility of our technique by correcting initial clock-skews of thousands of picoseconds with a granularity of 1.8 picoseconds. The theoretical work together with the experimental details developed in this book offer readers from the mixed-signal circuit field a comprehensive way to deal with clock-skew errors in future time-interleaved ADCs.

Autorentext

David Camarero received the BS Degree in Telecommunication Engineering from ETSETB, Barcelona, in 2002 and the MS Degree in Telecommunications Systems and the PhD Degree in Communications and Electronics from Telecom ParisTech, Paris, in 2003 and 2007, respectively. His research interests include signal processing and mixed-signal circuit design.