The SECD Microprocessor

This is a milestone in machine-assisted microprocessor verification. Gordon [20] and Hunt [32] led the way with their verifications of sim ple designs, Cohn [12, 13] followed this with the verification of parts of the VIPER microprocessor. This work illustrates how much these, and other, pioneers achieved in developing tractable models, scalable tools, and a robust methodology. A condensed review of previous re search, emphasising the behavioural model underlying this style of verification is followed by a careful, and remarkably readable, ac count of the SECD architecture, its formalisation, and a report on the organisation and execution of the automated correctness proof in HOL. This monograph reports on Graham's MSc project, demonstrat ing that - in the right hands - the tools and methodology for formal verification can (and therefore should?) now be applied by someone with little previous expertise in formal methods, to verify a non-trivial microprocessor in a limited timescale. This is not to belittle Graham's achievement; the production of this proof, work ing as Graham did from the previous literature, goes well beyond a typical MSc project. The achievement is that, with this exposition to hand, an engineer tackling the verification of similar microprocessor designs will have a clear view of the milestones that must be passed on the way, and of the methods to be applied to achieve them.

Inhalt
1 Formal Methods and Verification.- 1.1 Achievements in Hardware Verification.- 1.2 The HOL System.- 2 LispKit and the SECD Architecture.- 2.1 The Syntax of LispKit.- 2.2 The Interpretation of LispKit.- 2.3 SECD Architecture.- 2.4 LispKit to SECD Machine Code.- 2.5 Summary.- 3 SECD Architecture: Silicon Synthesis.- 3.1 Project Context.- 3.2 Levels of the Design.- 3.3 The Chip Interface.- 3.4 Internal Architecture and Microcode.- 3.5 The Final Layout.- 3.6 Summary and Status.- 4 Formal Specification of the SECD Design.- 4.1 Modelling Hardware.- 4.2 The Top Level Specification.- 4.3 The Low Level Definition.- 4.4 Register Transfer Level Specification.- 4.5 Relating the Levels.- 4.6 Summary.- 5 Verification of the SECD Design.- 5.1 Constraints.- 5.2 Structure of the Proof.- 5.3 Unfolding the System Definition.- 5.4 Phase Stage: Effect of Each Microinstruction.- 5.5 Microprogramming Stage: Symbolic Execution.- 5.6 Liveness.- 5.7 Computations across abstraction.- 5.8 Summary.- 6 Denouement.- 6.1 Putting the Proof Result into Context.- 6.2 Retrospective Improvements.- 6.3 Hardware Verification.