This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.

Autorentext
Dr.-Ing. Zheng Wang earned the Bachelor degree in physics from Shanghai Jiao Tong University (SJTU), China and Master degree in Electronic Engineering from Technische Universität München (TUM), Germany. From 2008 till 2009, he worked in the mobile sector of Infineon Technologies AG in Munich (currently Intel Mobile Communications). In 2010 he joined as a research associate in the Institute for Communication Technologies and Embedded Systems (ICE) of RWTH-Aachen University, Germany, where he obtained the PhD (Dr.-Ing.) in the year 2015. From 2015 till 2016, he worked in the Bio-inspired Reconfigurable Analog INtegrated (BRAIN) Systems Lab, Nanyang Technological University, Singapore in the field of neuromorphic ASIC and hardware security. In 2017 he joined the Center for Automotive Electronics, Shenzhen Institutes of Advanced Technology as an Assistant Professor.
Dr.-Ing. Wang's research interests include the design of digital processor and system, low-power and error-resilient architecture, hardware platform of neuromorphic computing. During PhD, he has published 20+ papers in well-known international conferences (e.g. DAC, DATE, GLSVLSI, ISCAS, ISQED). The reliability-aware high-level synthesis tool flow developed by him was demonstrated in DAC'13 and DAC'14. He has participated several international research projects funded by European Union, German Research Foundation, and Singaporean and Chinese grant agencies. He has successfully taped-out one mixed-signal Extreme Learning Machine (ELM) processor with 65nm CMOS technology, which achieves the peak performance of 1.2TOPS/W.

Inhalt

Introduction.- Background.- Related Work.- High-level Fault Injection and Simulation.- Architectural Reliability Estimation.- Architectural Reliability Exploration.- System-level Reliability Exploration.- Conclusion and Outlook.