RRAM technology has made significant progress in the past decade as a competitive candidate for the next generation non-volatile memory (NVM). This lecture is a comprehensive tutorial of metal oxide-based RRAM technology from device fabrication to array architecture design. State-of-the-art RRAM device performances, characterization, and modeling techniques are summarized, and the design considerations of the RRAM integration to large-scale array with peripheral circuits are discussed. Chapter 2 introduces the RRAM device fabrication techniques and methods to eliminate the forming process, and will show its scalability down to sub-10 nm regime. Then the device performances such as programming speed, variability control, and multi-level operation are presented, and finally the reliability issues such as cycling endurance and data retention are discussed. Chapter 3 discusses the RRAM physical mechanism, and the materials characterization techniques to observe the conductive filaments and the electrical characterization techniques to study the electronic conduction processes. It also presents the numerical device modeling techniques for simulating the evolution of the conductive filaments as well as the compact device modeling techniques for circuit-level design. Chapter 4 discusses the two common RRAM array architectures for large-scale integration: one-transistor-one-resistor (1T1R) and cross-point architecture with selector. The write/read schemes are presented and the peripheral circuitry design considerations are discussed. Finally, a 3D integration approach is introduced for building ultra-high density RRAM array. Chapter 5 is a brief summary and will give an outlook for RRAM's potential novel applications beyond the NVM applications.

Autorentext

Shimeng Yu received his B.S. degree in microelectronics from Peking University, Beijing, China, in 2009, and his M.S. degree and Ph.D. degree in electrical engineering from Stanford University, Stanford, CA, in 2011, and 2013, respectively. He did summer internships in IMEC, Belgium, in 2011, and IBM TJ Watson Research Center in 2012. He is currently an assistant professor of electrical engineering and computer engineering at Arizona State University, Tempe, AZ U.S. His research interests are emerging nano-devices and circuits with focus on the resistive switching memories, and new computing paradigms with focus on the neuro-inspired computing. He has published over 40 journal papers and over 80 conference papers with citations of 2500 and H-index 25 by 2015. He was awarded the Stanford Graduate Fellowship from 2009âEUR"2012, the IEEE Electron Devices Society Masters Student Fellowship in 2010, the IEEE Electron Devices Society Ph.D. Student Fellowship in 2012, the DoD DTRA Young Investigator Award in 2015, and the NSF CAREER Award in 2016. He has been serving on the Technical Committee of Nanoelectronics and Gigascale Systems, IEEE Circuits and Systems Society since 2014.