The Student's Guide to VHDL

The Student's Guide to VHDL is a condensed edition of The Designer's Guide to VHDL, the most widely used textbook on VHDL for digital system modeling. The Student's Guide is targeted as a supplemental reference book for computer organization and digital design courses.

Since publication of the first edition of The Student's Guide, the IEEE VHDL and related standards have been revised. The Designer's Guide has been revised to reflect the changes, so it is appropriate that The Student's Guide also be revised.
In The Student's Guide to VHDL, 2nd Edition, we have included a design case study illustrating an FPGA-based design flow. The aim is to show how VHDL modeling fits into a design flow, starting from high-level design and proceeding through detailed design and verification, synthesis, FPGA place and route, and final timing verification. Inclusion of the case study helps to better serve the educational market. Currently, most college courses do not formally address the details of design flow. Students may be given informal guidance on how to proceed with lab projects. In many cases, it is left to students to work it out for themselves. The case study in The Student's Guide provides a reference design flow that can be adapted to a variety of lab projects.

Autorentext

Peter J. Ashenden received his B.Sc.(Hons) and Ph.D. from the University of Adelaide, Australia. He was previously a senior lecturer in computer science and is now a Visiting Research Fellow at the University of Adelaide. His research interests are computer organization and electronic design automation. Dr. Ashenden is also an independent consultant specializing in electronic design automation (EDA). He is actively involved in IEEE working groups developing VHDL standards, is the author of The Designer's Guide to VHDL and The Student's Guide to VHDL and co-editor of the Morgan Kaufmann series, Systems on Silicon. He is a senior member of the IEEE and a member of the ACM.

Inhalt

Preface
1 Fundamental Concepts
2 Scalar Data Types and Operations
3 Sequential Statements
4 Composite Data Types and Operations
5 Basic Modeling Constructs
6 Subprograms
7 Packages and Use Clauses
8 Aliases
9 Resolved Signals
10 Generics
11 Components
12 Generate Statements
13 Design for Synthesis
14 Case Study: System Design using the Gumnut Core
A Standard Packages
B VHDL Syntax
C Differences Among VHDL Versions
D Answers to Exercises
References
Index