Heterogeneous Integrations

Heterogeneous integration uses packaging technology to integrate dissimilar chips, LED, MEMS, VCSEL, etc. from different fabless houses and with different functions and wafer sizes into a single system or subsystem. How are these dissimilar chips and optical components supposed to talk to each other? The answer is redistribution layers (RDLs). This book addresses the fabrication of RDLs for heterogeneous integrations, and especially focuses on RDLs on: A) organic substrates, B) silicon substrates (through-silicon via (TSV)-interposers), C) silicon substrates (bridges), D) fan-out substrates, and E) ASIC, memory, LED, MEMS, and VCSEL systems. The book offers a valuable asset for researchers, engineers, and graduate students in the fields of semiconductor packaging, materials sciences, mechanical engineering, electronic engineering, telecommunications, networking, etc.

Autorentext
SPECIALIZED PROFESSIONAL COMPETENCE
Design, analysis, materials, process, manufacturing, qualification, reliability, testing, and thermal management of electronic and optoelectronic components and systems. SMT, fan-out and fan-in WLP, TSV, 3D IC Integration, heterogeneous integration and SiP. Leadfree soldering, manufacturing, and solder joint reliability. Management of a R&D Laboratory and Company. BACKGROUND AND PROFESSIONAL EXPERIENCE

Ph.D. (Theoretical and Applied Mechanics), University of Illinois, Urbana, IL (1977) M.S. (Engineering Physics), University of Wisconsin, Madison, WI (1974)

M.S. (Structural Mechanics), University of British Columbia, Vancouver, BC (1973)

M.S. (Management Science), Fairleigh Dickinson University, Teaneck, NJ (1981)

B.S. (Civil Engineering), National Taiwan University, Taipei, Taiwan (1970)

ASM Pacific Technology (Sr. Technical Advisor), Hong Kong, July 2014 - Present

Industrial Technology Research Institute (ITRI Fellow), Taiwan, Jan 2010 June 2014

Hong Kong University of Science & Technology (Visiting Professor), Jan 2009 Jan 2010

Institute of Microelectronic, (Director, System Packaging Lab), Singapore, 2006 - Jan 2009

Agilent Technologies, Inc. (Sr. Interconnection Specialist), Santa Clara, CA, 2000-2006 Express Packaging Systems, Inc., (President), Palo Alto, CA, 1995-2000

Hewlett-Packard Labs/Company (Senior MTS/Individual Contributor), Palo Alto, CA, 1984-1995

Sandia National Laboratories (Member of Technical Staff), Albuquerque, NM, 1982-1983

Bechtel Power Corporation (Lead Engineer), San Francisco, CA, 1981-1982

Ebasco (Lead Engineer), New York, NY, 1978-1980

Exxon Production and Research Company (Research Engineer), Houston, TX, 1977-1978

Editorial Board of ASME Transactions, Journal of Electronic Packaging, 1989-1999

Editorial Board of IEEE Transactions on Components, Packaging, Manufacture Technology, 1990-1995

Editor-in-Chief, Circuit World, 1998-2000.

Program Chair ('90) to General Chair ('92) of the IEEE/CPMT IEMTS

Program Chair ('93) to General Chair ('95) of the IEEE/CPMT ECTC

Publication Chair for IEEE/ECTC

Symposium Organizer/Chair of the ASME Winter Annual Meeting, 1987-2002

ASME Distinguish Lecturer (2000-2003), IEEE/CPMT Distinguish Lecturer (1998-present)

ASME Worcester Reed Warner Medal (2015)

IEEE Components Packaging and Manufacturing Technology Field Award (2013)

IMAPS William Ashman Achievement Award (2013)

Pan Wen Yuan Distinguished Research Award (2011)

IEEE/CPMT Outstanding Sustained Technical Contribution Award (2010)

Best IEEE Transactions Paper Award (2010 Components Packaging and Manufacturing Technology)

Outstanding Paper Award (2009 IEEE EPTC)

SME Total Excellence in Electronics Manufacturing Award (2001)

Best ASME Transactions Paper Award (2000 Journal of Electronic Packaging)

IEEE/CPMT Outstanding Contribution Awards (2000)

IEEE Meritorious Achievement Award in Continuing Education (2000)

ASME/EEP Technical Achievement Award (1998)

IEEE/CPMT Manufacturing Awards (1994)

Best of Conference Paper Award (1989 IEEE ECTC)

IEEE Fellow (since 1994), ASME Fellow (since 1999), IMAPS Fellow (since 2013)

Over 20 books, 470 peer-reviewed papers, 30 issued and pending patents, and 290 keynotes/lectures.

Inhalt

Chapter 1. Overview of 3D IC Heterogeneous Integrations.- Chapter 2. RDLs for Heterogeneous Integrations on Organic Substrates.- Chapter 3. RDLs for Heterogeneous Integration on Silicon (TSV-Interposers).- Chapter 4. RDLs for Heterogeneous Integration on Silicon (Bridges).- Chapter 5. RDLs for Heterogeneous Integration on Fan-Out Substrates.- Chapter 6. 3D IC Heterogeneous Integration in Memory Stacking.- Chapter 7. 3D IC Heterogeneous Integration in PoP Formats.- Chapter 8. 3D IC Heterogeneous Integration in Chip-to-Chip Formats.- Chapter 9. 3D IC Heterogeneous Integration with LED and VCSEL.- Chapter 10. Future Trends of 3D IC Heterogeneous Integrations.