Rapid Prototyping of Digital Systems, Second Edition provides an exciting and challenging laboratory component for an undergraduate digital logic design class. The more advanced topics and exercises are also appropriate for consideration at schools that have an upper level course in digital logic or programmable logic. Design engineers working in industry will also want to consider this book for a rapid introduction to FPLD technology and logic synthesis using commercial CAD tools, especially if they have not had previous experience with the new and rapidly evolving technology. Two tutorials on the Altera CAD tool environment, an overview of programmable logic, and a design library with several easy-to-use input and output functions were developed for this book to help the reader get started quickly. Early design examples use schematic capture and library components. VHDL is used for more complex designs after a short introduction to VHDL-based synthesis. A coupon is included with the text for purchase of the new UP 1X board. The additional logic and memory in the UP 1X's FLEX 10K70 is useful on larger design projects such as computers and video games. The second edition includes an update chapter on programmable logic, new robot sensors and projects, optional Verilog examples, and a meta assembler which can be used to develop assemble language programs for the computer designs in Chapters 8 and 13.

Inhalt

1. Tutorial I: The 15 Minute Design. 2. The Altera UP 1 and UP 1X CPLD Boards. 3. Programmable Logic Technology. 4. Tutorial II: Sequential Design and Hierarchy. 5. UP1core Library Functions. 6. Using VHDL for Synthesis of Digital Hardware. 7. State Machine Design: The Electric Train Controller. 8. A Simple Computer Design: The muP 1. 9. VGA Video Display Generation. 10. Communications: Interfacing to the PS/2 Keyboard. 11. Communications: Interfacing to the PS/2 Mouse. 12. Robotics: The UP1-bot. 13. A RISC Design: Synthesis of the MIPS Processor Core. Appendices. Glossary. Index. About the Accompanying CD-Rom.