Metric Driven Design Verification

Exponentially increasing design complexity has necessitated the adoption of metric driven planning and project management. Metric Driven Design Verification provides the semiconductor industry's first metric driven based approach to functional verification. A metric based flow is described that focuses on the four steps of: 1. Planning: Defining what needs to be done and the automatically trackable metrics that will be used to measure progress. 2. Execution: Implementing verification environments and then extensively exercising the device under verification utilizing comprehensive, massively parallel regression strategies. 3. Measurement: Automatically capturing the metrics defined in planning to provide objective data with which to manage the verification project. Custom tailoring those metrics through an automated reporting framework to provide all stakeholders a real-time meaningful view of project status. 4. Response: Utilizing the returned metrics to effectively adapt to changing project conditions. Making use of automated response mechanisms to automate engineering processed and management response to streamline project management processes. The primary audience for this book is professional engineers, managers, and executives. It is written in an easily understandable style and consists of four parts. The first three parts are tailored for executives, engineering managers, and engineers respectively. The fourth part presents case studies and commentaries from industry luminaries and experts on metric driven verification. Metric Driven Design Verification brings together the best practices and real-life experiences of several leading electronic companies worldwide in planning and managing verification projects, while automating critical processes. It addresses all aspects of verification and summarizes the different options available to engineers, managers and executives.

Résumé

Verification Projects: Planning to Closure addresses the challenges of functional verification in the digital semiconductor market today. It presents best practices by alternately looking at the verification problem as a complete system, and expounding on the best practices for executing with the myriad of available verification technologies. As a result, the reader gains not only a sufficient knowledge to use each technology intelligently, but more importantly, knowledge of when each technology can be used most effectively, and how to combine the various technologies to provide the best verification solution for their project.

All of this information is conveyed within the framework of the leading edge plan to closure methodology. This methodology conveys three important messages:

• Effective planning of the verification effort using well-defined measurable objectives to gauge the project status as it proceeds. It is shown that this planning is valuable for tracking and reacting to project status, (of more importance, and far more emphasized in the management book). Furthermore, and, more importantly here, we show that planning helps ensure that the right verification environment is built the first time using optimal tool and resource selections. We also show that appropriate planning significantly reduces the amount of effort put into verification, (currently estimated to be about 70% of the complete project effort).

• By using appropriate horizontal re-use methodologies, project quality, productivity, and predictability can be greatly enhanced. These methodologies include how to best design and package verification intellectual property so that it can be re-used from project to project.

• By using appropriate vertical re-use methodologies, project quality, productivity, and predictability can be greatly enhanced. These methodologies are discussed including how to best design and package verification intellectual property so that projects can benefit by effectively using each level of verification as building blocks for successive levels throughout the project. For example, how to best re-use of block level environments at the chip level, how to best architect environments so that they can be easily used in both simulators and emulators, and how to design environments so that they can easily facilitate system level modeling, RTL verification and software verification.

It is important to note that while this book will touch on all available verification technologies, it is not meant to be an in-depth training manual on any one technology. That level of material has been well covered in other books. The intent of this book is to teach the user a fundamental understanding of each technology, teach the user how to best employ each technology and teach the user how to execute most effectively with these technologies using a plan to closure methodology.

Contenu
Analyzing And Driving Verification: An Executive's Guide.- The Verification Crisis.- Automated Metric-Driven Processes.- Roles in a Verification Project.- Overview of a Verification Project.- Verification Technologies.- Managing The Verification Process.- Verification Planning.- Capturing Metrics.- Regression Management.- Revision Control and Change Integration.- Debug.- Executing The Verification Process.- Coverage Metrics.- Modeling and Architectural Verification.- Assertion-Based Verification.- Dynamic Simulation-Based Verification.- System Verification.- Mixed Analog and Digital Verification.- Design for Test.- Case Studies And Commentaries.- Metric-Driven Design Verification: Why Is My Customer a Better Verification Engineer Than Me?.- Metric-Driven Methodology Speeds the Verification of a Complex Network Processor.- Developing a Coverage-Driven SoC Methodology.- From Panic-Driven to Plan-Driven Verification Managing the Transition.- Verification of a Next-Generation Single-Chip Analog TV and Digital TV ASIC.- Management IP: New Frontier Providing Value Enterprise-Wide.- Adelante VD3204x Core, SubSystem, and SoC Verification.- SystemC-based Virtual SoC: An Integrated System-Level and Block-Level Verification Approach from Simulation to Coemulation.- Is Your System-Level Project Benefiting from Collaboration or Headed to Chaos?.