OPTIMIZATION OF LEAKAGE POWER USING COMMON POWER FORMAT

As the industry moves to 65 nanometers and below, the challenges related to the design and manufacture of low-power products have increased exponentially. In response to these challenges, the Common Platform technology collaborators and Cadence Design Systems have developed a 65nm low-power reference flow using the Si2 Common Power Format (CPF) standard to provide a single specification of low-power intent throughout the flow. This paper explains how CPF (Common Power Format) methodology can be used to optimize leakage power effectively compared to ad-hoc methods and CPF enabled tools can be used to implement and verify that the low power features works seamlessly throughout the design flow. The paper will illustrate how the specification of design features such as Power Shut Off (PSO), State Retention (SR) Registers and Isolation (ISO) Cells can be inserted & verified and the advantages of using a CPF based flow over an ad-hoc solution.

Auteur

DR.SHREESHA KALKOOR M was born in Udupi city, Karnataka, India in 1981. He received the B.E degree in ECE in 2002 and M.Tech degree in Digital Electronics and Communication in 2010 from Visvesvaraya Technological University, Belagavi, Karnataka, India. He received the Ph.D. degree in ECE from Sunrise University, Alwar, Rajasthan, India, in 2018.