Synchronization Design for Digital Systems

Synchronization is one of the important issues in digital system design. While other approaches have always been intriguing, up until now synchro nous operation using a common clock has been the dominant design philo sophy. However, we have reached the point, with advances in technology, where other options should be given serious consideration. This is because the clock periods are getting much smaller in relation to the interconnect propagation delays, even within a single chip and certainly at the board and backplane level. To a large extent, this problem can be overcome with care ful clock distribution in synchronous design, and tools for computer-aided design of clock distribution. However, this places global constraints on the design, making it necessary, for example, to redesign the clock distribution each time any part of the system is changed. In this book, some alternative approaches to synchronization in digital sys tem design are described and developed. We owe these techniques to a long history of effort in both digital system design and in digital communica tions, the latter field being relevant because large propagation delays have always been a dominant consideration in design. While synchronous design is discussed and contrasted to the other techniques in Chapter 6, the dom inant theme of this book is alternative approaches.

Contenu
Preface.- Acknowledgements.- 1 Introduction.- 1.1 Asynchronous and Synchronous Design.- 1.2 Motivation for Asynchronous Design.- 1.3 Plan of the Book.- 2 Synchronization.- 2.1 Synchronization in Digital Systems.- 2.2 Abstraction in Synchronization.- 2.3 Timing Abstraction in Digital Systems.- 3 Synthesis of Self-Timed Circuits.- 3.1 An Interconnection Scheme.- 3.2 Circuit Behavioral Description.- 3.3 Interconnection Circuit Specifications.- 3.4 Weakest Semi-Modular Constraints.- 3.5 Synthesis Procedure and the C-Element.- 3.6 Interconnection Design Examples.- 4 Self-Timed Programmable Processors.- 4.1 A Programmable Signal Processor.- 4.2 Data Flow Control.- 4.3 Program Flow Control.- 4.4 Processor Architecture.- 4.5 simulation and performance evaluation.- 5 A Chip Set for Adaptive Filters.- 5.1 Properties of Self-Timed Designs.- 5.2 A Self-Timed Array Multiplier.- 5.3 A Vectorized Adaptive Lattice Filter.- 5.4 Performance Evaluation.- 6 Isochronous Interconnect.- 6.1 Synchronous Interconnect.- 6.2 Anisochronous Interconnect.- 6.3 Synchronization in Digital Communication.- 6.4 Non-Synchronous Interconnect.- 6.5 Architectural Issues.- 6.6 Conclusions.- 7 Automatic Verification.- 7.1 Verification of Self-Timed Circuits.- 7.2 Trace Theory of Finite Automata.- 7.3 Tree Arbiter.- 7.4 Arbiter with Reject.- 7.5 Performance Summary.- Permuted Index.