VLSI Planarization

At the beginning we would like to introduce a refinement. The term 'VLSI planarization' means planarization of a circuit of VLSI, Le. the embedding of a VLSI circuit in the plane by different criteria such as the minimum number of connectors, the minimum total length of connectors, the minimum number of over-the-element routes, etc. A connector is designed to connect the broken sections of a net. It can be implemented in different ways depending on the technology. Connectors for a bipolar VLSI are implemented by diffused tun nels, for instance. By over-the-element route we shall mean a connection which intersects the enclosing rectangle of an element (or a cell). The possibility of the construction such connections during circuit planarization is reflected in element models and can be ensured, for example, by the availability of areas within the rectangles where connections may be routed. VLSI planarization is one of the basic stages (others will be discussed below) of the so called topological (in the mathematical sense) approach to VLSI design. This approach does not lie in the direction of the classical approach to automation of VLSI layout design. In the classical approach to computer aided design the placement and routing problems are solved successively. The topological approach, in contrast, allows one to solve both problems at the same time. This is achieved by constructing a planar embedding of a circuit and obtaining the proper VLSI layout on the basis of it.

Klappentext

At the beginning we would like to introduce a refinement. The term 'VLSI planarization' means planarization of a circuit of VLSI, Le. the embedding of a VLSI circuit in the plane by different criteria such as the minimum number of connectors, the minimum total length of connectors, the minimum number of over-the-element routes, etc. A connector is designed to connect the broken sections of a net. It can be implemented in different ways depending on the technology. Connectors for a bipolar VLSI are implemented by diffused tun­ nels, for instance. By over-the-element route we shall mean a connection which intersects the enclosing rectangle of an element (or a cell). The possibility of the construction such connections during circuit planarization is reflected in element models and can be ensured, for example, by the availability of areas within the rectangles where connections may be routed. VLSI planarization is one of the basic stages (others will be discussed below) of the so called topological (in the mathematical sense) approach to VLSI design. This approach does not lie in the direction of the classical approach to automation of VLSI layout design. In the classical approach to computer­ aided design the placement and routing problems are solved successively. The topological approach, in contrast, allows one to solve both problems at the same time. This is achieved by constructing a planar embedding of a circuit and obtaining the proper VLSI layout on the basis of it.

Zusammenfassung
`Altogether, the book is very well written and a good piece of work. All the notions are clearly defined and the proofs are presented in detail. Many pictures illustrate the subjects discussed and help to make things clear and understandable.'
Mathematical Reviews, 98m

Inhalt
1 Discrete Mathematics Fundamentals.- 1.1 Graphs And Hypergraphs.- 1.2 Algorithms And Their Complexity.- 1.3 Algorithms In Graphs.- 1.4 Intractable Problems.- 2 Graph Planarization.- 2.1 Planar Graphs. Graph Planarity Criteria.- 2.2 Graph Planarity Testing Algorithms.- 2.3 Approximation Algorithm for Graph Planarization.- 3 Hypergraph Planarization.- 3.1 The Concept of Planar Hypergraph.- 3.2 Planarity of Different Hypergraph Classes.- 3.3 Hypergraph Nonplanarity Measures. Statement of Hypergraph Planarization Problem.- 3.4 Decomposition Methods of Hypergraph Planarization.- 4 Mathematical Models for VLSI Planarization Problem.- 4.1 Graph versus Hypergraph VLSI Models.- 4.2 VLSI Models with Specified Element Models.- 4.3 Dynamic VLSI Models.- 5 Extracting a Maximum Planar VLSI Part.- 5.1 Extracting a Maximum Planar VLSI Part as a Hypergraph Planarization Problem.- 5.2 Iteration Algorithm for Hypergraph Planarization.- 5.3 Hypergraph Planarization by Konig Representation.- 5.4 Operations of Local Embedding Optimization.- 6 Constructing Nonplanar Connections.- 6.1 Graph Model for Nonplanar Connections.- 6.2 Constructing a Nonplanar Connection as a Steiner Problem in a Weighted Graph.- 6.3 Ordering Nonplanar Connections to be Constructed.- 7 Planarization System Structure.- 7.1 Purpose and Functions of the System.- 7.2 Planarization System Structure. Logic Diagram.- 7.3 Data Organization in Planarization System.- 7.4 Some Aspects of the Practical Use of the Planarization System.- References.