Layout Minimization of CMOS Cells

The layout of an integrated circuit (lC) is the process of assigning geometric shape, size and position to the components (transistors and connections) used in its fabrication. Since the number of components in modem ICs is enormous, computer aided-design (CAD) programs are required to automate the difficult layout process. Prior CAD methods are inexact or limited in scope, and produce layouts whose area, and consequently manufacturing costs, are larger than necessary. This book addresses the problem of minimizing exactly the layout area of an important class of basic IC structures called CMOS cells. First, we precisely define the possible goals in area minimization for such cells, namely width and height minimization, with allowance for area-reducing reordering of transistors. We reformulate the layout problem in terms of a graph model and develop new graph-theoretic concepts that completely characterize the fundamental area minimization problems for series-parallel and nonseries-parallel circuits. These concepts lead to practical algorithms that solve all the basic layout minimization problems exactly, both for a single cell and for a one-dimensional array of such cells. Although a few of these layout problems have been solved or partially solved previously, we present here the first complete solutions to all the problems of interest.

Klappentext

Presents new and provable optimal solutions to a number of previously unsolved problems in minimizing the layout area of CMOS cells and cell arrays, an important aspect of integrated circuit design. Shows how these problems can be solved using exact algorithms, suitable for incorporation into comput

Inhalt
I. Introduction.- 1.1 Problem and Motivation.- 1.2 Layout Styles.- 1.3 Functional Cell Optimization.- 1.4 Proposed Approach.- II. Functional Cell Layout Methods.- 2.1 Functional Cell Design.- 2.2 Survey of Prior Methods.- 2.3 Critique of Prior Work.- III. Series-Parallel Cell Width Minimization.- 3.1 Graph Optimization Problems.- 3.2 Theory of Dual Trail Covering.- 3.3 Optimal Trail Covering without Reordering.- 3.4 Optimal Trail Covering with Reordering.- 3.5 Analysis of Complete Class of Practical Cells.- 3.6 Minimum-Width Rows of Cells.- IV. Planar Cell Width Minimization.- 4.1 Nonseries-Parallel Composition.- 4.2 P-TrailTrace Algorithm.- 4.3 Complete Study of Practical Planar Cells.- V. Single Cell Width and Height Minimization.- 5.1 Layout Problem.- 5.2 Extension of Series-Parallel Cell Theory.- 5.3 HR-TrailTrace Algorithm.- 5.4 Complete Study of Practical Cells.- 5.5 Planar Cell Layout.- VI. Cell Array Width and Height Minimization.- 6.1 Layout Problem.- 6.2 HRM-TrailTrace Algorithm.- 6.3 Experimental Results.- VII. Conclusions.- 7.1 Contributions.- 7.2 Practical Applications and Extensions.