High-Level System Modeling

A reactive system is one that is in continual interaction with its environment and executes at a pace determined by that environment. Examples of reactive systems are network protocols, air-traffic control systems, industrial-process control systems etc. Reactive systems are ubiquitous and represent an important class of systems. Due to their complex nature, such systems are extremely difficult to specify and implement. Many reactive systems are employed in highly-critical applications, making it crucial that one considers issues such as reliability and safety while designing such systems. The design of reactive systems is considered to be problematic, and p.oses one of the greatest challenges in the field of system design and development. In this paper, we discuss specification-modeling methodologies for reactive systems. Specification modeling is an important stage in reactive system design where the designer specifies the desired properties of the reactive system in the form of a specification model. This specification model acts as the guidance and source for the implementation. To develop the specification model of complex systems in an organized manner, designers resort to specification modeling methodologies. In the context of reactive systems, we can call such methodologies reactive-system specification modeling methodologies.

Inhalt

1. Specification-Modeling Methodologies for Reactive-System Design.- 1.1. Introduction.- 1.2. Characteristics of Reactive Systems.- 1.3. Specification-Modeling Methodology Requirements.- 1.4. Specification-Modeling Methodology for Reactive Systems.- 1.5. A Survey of Methodologies.- 1.6. Summary.- 1.7. Recommendations.- 1.8. Conclusions.- 2. Survey on Languages for Object Oriented Hardware Design Methodologies.- 2.1. Introduction.- 2.2. Introduction to Object-Oriented Design.- 2.3. Possible Approaches.- 3. VSPEC: A Declarative Requirements Specification Language for VHDL.- 3.1. Introduction.- 3.2. Important VHDL Constructs.- 3.3. The VSPEC Clauses.- 3.4. Formal Representation of VSPEC.- 3.5. Extended Example: 16-bit Move Machine.- 3.6. Related Work.- 3.7. Current Status and Future Directions.- 4. Communication Protocols Implemented in Hardware: VHDL Generation from Estelle.- 4.1. Introduction.- 4.2. VHDL versus Estelle Semantics.- 4.3. Estelle to VHDL Translation Model.- 4.4. Conclusions.- 5. An Algorithm for the Translation of SDL into Synthesizable VHDL.- 5.1. Introduction.- 5.2. The SDL Subset.- 5.3. Synthesis Constraints.- 5.4. The Mapping Algorithm.- 5.5. Structure.- 5.6. Data Definition.- 5.7. Process Communication.- 5.8. Process Behaviour.- 5.9. Variable Declaration.- 5.10. Example of Implementation.- 5.11. Conclusion.- 6. From LOTOS to VHDL.- 6.1. Introduction.- 6.2. Languages.- 6.3. Translation.- 6.4. Conclusion.- 6.5. Appendix: A Complete Example.- 7. Using an X-Machine to Model a Video Cassette Recorder.- 7.1. Introduction.- 7.2. The Basic Model.- 7.3. Extending the Machine to handle Fast-forward and Rewind Operations.- 7.4. Programming the VCR.- 7.5. Combining the Parts of the Model.- 7.6. Adding a Model of the Video Tape.- 7.7. Animation and Execution of theSpecification.- 7.8. Verification Issues.- 7.9. Evaluation and Conclusion.